Digital Control and Sampling

Q: How fast should I sample?

At least 10 samples per closed-loop rise time, and not slower than a quarter of the dead time. Faster than that costs processor time and amplifies noise without improving control.

Q: What is aliasing?

A frequency above half the sample rate appears in the samples as a false lower frequency. Prevent it with an analog low-pass filter before the converter.

Q: Why does my loop get worse when the PLC scan time grows?

Each sample is extra delay. If the loop is in a program with a variable scan time (or an uneven task period) the effective sample time and the delay both change.

Q: Z-transform or just program it?

For most PID work you can program the discrete equations directly. The Z-transform is for designing and analyzing sampled loops, such as a dead-beat controller or a filter.

Sample time, aliasing, delay, the Z-transform, discrete PID and choosing a sample rate.

On this page

From continuous to sampled
Sampling and aliasing
Choosing the sample time
Worked example: sample time on the oven loop
Discretizing a controller and a plant
The discrete PID algorithm
Quantization and word length
FAQ

From continuous to sampled

Almost every controller today is a program: a PLC, a microcontroller, a drive. It reads the sensor at regular instants (every T_s), computes the control law and holds the output constant until the next instant with a zero-order hold (ZOH). Between samples the loop is open. The analysis of the earlier pages (Laplace Transforms and Transfer Functions to Stability: Routh, Root Locus and Margins) still applies if T_s is short compared with the dynamics, but it shows up in two new ways: aliasing and an additional delay of about T_s ÷ 2.

Sampling and aliasing

The Nyquist–Shannon theorem says a signal can be reconstructed from its samples only if it is sampled at more than twice its highest frequency (f_s > 2 f_max). A component at frequency f above half the sampling rate aliases, appearing in the samples as a false low-frequency component at |f − k f_s| for the integer k that brings it into the range 0 to f_s ÷ 2. The cure is an analog anti-aliasing filter before the converter, or sampling much faster than needed and filtering digitally.

Signal	Sample rate	Appears as	Comment
50 Hz mains pick-up	40 Hz	10 Hz	a slow wobble on the measurement
50 Hz mains pick-up	100 Hz	50 Hz	exactly at the Nyquist frequency: unreliable
60 Hz pick-up	100 Hz	40 Hz	aliases into the passband
vibration of 130 Hz	100 Hz	30 Hz	a low-frequency ghost in a slow loop
1 Hz ripple	1 000 Hz	1 Hz	recorded correctly

Choosing the sample time

Each sample adds a delay: the ZOH holds the output for T_s, which on average is a delay of T_s ÷ 2, and the measurement is up to T_s old. This erodes the phase margin by ω_gc T_s ÷ 2 (see Frequency Response and Bode Plots). Rules of thumb: sample at least 10 times per closed-loop rise time, or 4 to 10 times per dead time, and at 10 to 30 times the closed-loop bandwidth for a servo. Typical rates:

Loop	Sample time
Temperature, level, slow chemical processes	0.5 to 5 s
Flow and pressure	0.05 to 0.5 s
Motor speed loop	0.5 to 2 ms
Position loop in a servo	0.25 to 1 ms
Motor current loop	50 to 100 µs (10 to 20 kHz)
Power converter control	10 to 50 µs

Worked example: sample time on the oven loop

Worked example: the Ziegler–Nichols PID at different sample times

The oven has a dead time of 15 s and the closed-loop rise time is about 46 s, so the rules give T_s ≤ 3.75 s (a quarter of the dead time) and ≤ 4.6 s (a tenth of the rise): 1 to 2 s is comfortable.
The ZN PID has a continuous phase margin of 37° at ω_gc = 0.081 rad/s. Each sample time costs ω_gc T_s ÷ 2 in phase; at T_s = 10 s this is 23°:

Sample time	Phase margin (estimated)	Overshoot (simulated)	IAE
1 s	35°	15 %	689
2 s	33°	17 %	705
5 s	26°	14 %	778
10 s	14°	26 %	1 237
15 s	2°	57 %	2 681
20 s	-9°	69 %	2 886

The same PID sampled every 1, 10 and 20 seconds.

At 1 s the loop behaves like the continuous design. By 10 s the loop rings noticeably, and at 20 s (more than the dead time) the response is badly oscillatory: the controller no longer sees what is happening between samples, and the extra delay has used up the margin. The slower the sample, the more conservative the tuning must be.

Discretizing a controller and a plant

A continuous plant sampled with a ZOH has an exact discrete equivalent. For the first-order oven part (ignoring its dead time) with T_s seconds: y_k+1 = a y_k + K (1 − a) u_k with a = e^{−T_s ÷ τ}. At T_s = 1 s, a = 0.99170 and the gain factor K (1 − a) = 0.01660; at 20 s, a = 0.8465. The pole of the discrete system lies at z = a inside the unit circle, so the plant is stable; the z-plane is the sampled counterpart of the s-plane: the left half-plane maps to the inside of the unit circle (z = e^{s T_s}), and stability requires all poles inside it.

To turn a continuous controller into a program, replace the derivative and integral by approximations: forward Euler (s ≈ (z − 1) ÷ T_s, simple but it can be unstable if T_s is large: the first-order lag above is stable only for T_s < 2 τ = 240 s), backward Euler (always stable, slightly damped) and the Tustin (bilinear) transform s ≈ (2 ÷ T_s)(z − 1) ÷ (z + 1) (a good match to the frequency response, preserving stability; the factor is 2 ÷ s at T_s = 1 s). For a digital design the more accurate method is to design directly in the z-domain.

The discrete PID algorithm

A typical positional implementation, executed every T_s:

e_k = r_k − y_k
P_k = K_p e_k
I_k = I_k−1 + K_p (T_s ÷ T_i) e_k (with anti-windup: skip the update when the output is saturated, see Practical Control: Windup, Feedforward and Cascade)
D_k = α D_k−1 − K_p T_d (1 − α) (y_k − y_k−1) ÷ T_s with α = T_d ÷ (T_d + N T_s) (derivative on the measurement, filtered)
u_k = clamp(P_k + I_k + D_k)

For the lambda PI of the oven with T_s = 1 s the integral increment per sample is K_p T_s ÷ T_i × e = 2 × 1 ÷ 120 = 0.0167 per °C of error per second. The velocity (incremental) form computes the change Δu_k and adds it to the previous output; it needs no integral state and handles bumpless switching and saturation naturally. Execution must be regular (a fixed-period task or interrupt): a PLC that runs the loop in a cyclic task with jitter violates the sample-time assumption.

Quantization and word length

The analog-to-digital converter (ADC) has finite resolution: an N-bit converter over a range R has a step q = R ÷ 2^N. The error is not a problem for P and I terms but is amplified by the derivative:

ADC	Step over 0 to 400 °C	Derivative term jitter (Z–N PID, no filter, T_s = 1 s)
10 bit	0.3906 °C	14.06 %
12 bit	0.0977 °C	3.52 %
16 bit	0.0061 °C	0.22 %

A 10-bit input makes the heater output jump by 14 percent per one-step change of the reading: the derivative must be filtered or the resolution increased. In a fixed-point controller, scaling and overflow also matter; in a 16-bit integer integral term a small T_s ÷ T_i may round to zero (the integral never grows): use 32-bit or floating-point for the integral.

Previous: Stability: Routh, Root Locus and Margins. Next: Practical Control: Windup, Feedforward and Cascade.
Embedded Systems for timers and fixed-rate tasks, and Data Logging for sampling and aliasing.
PLC and Logic Control for cyclic tasks.
Control Systems: the whole guide.

FAQ

How fast should I sample?

At least 10 samples per closed-loop rise time, and not slower than a quarter of the dead time. Faster than that costs processor time and amplifies noise without improving control.

What is aliasing?