Digital Logic

Digital circuits work with two voltage levels, called 0 (low) and 1 (high), and combine them with gates to make decisions, count, store and move data. Everything from a microcontroller to a computer is built from them. Even if you only use microcontrollers, a few logic chips (a level shifter, a shift register, a decoder, a gate that debounces) turn up in nearly every project, and the same ideas explain how a PLC’s ladder logic and a processor’s instructions work.

Binary and hexadecimal

A bit is one binary digit. Four bits make a nibble (16 values, one hexadecimal digit), eight make a byte (256 values), and so on: n bits give 2ⁿ values. Hexadecimal (base 16, digits 0–9 and A–F) is a compact way to write binary: each hex digit is exactly four bits.

Decimal	Binary	Hex	Notes
0	0000	0
5	0101	5
9	1001	9	Largest BCD digit
10	1010	A
15	1111	F	A full nibble
183	1011 0111	B7	Each hex digit is one nibble: B = 1011, 7 = 0111
255	1111 1111	FF	A full byte

Convert 0xB7 to decimal: B × 16 + 7 = 11 × 16 + 7 = 183. The site’s Bitwise and Register Field Calculator converts and manipulates values for you. A signed byte uses two’s complement: the top bit has weight −128, so 0xFF is −1 (see Networking Fundamentals).

Gates and truth tables

A gate is a circuit that gives one output from one or more inputs according to a rule. A truth table lists the output for every combination of inputs: n inputs give 2ⁿ rows. Six gates cover almost everything.

Gate	Output is 1 when…	Typical use
AND	all inputs are 1	Enabling: a signal passes only when a second input allows it
OR	any input is 1	Combining alarms or start conditions
NOT (inverter)	the input is 0	Reversing a level; buffering
NAND	any input is 0 (not all are 1)	The universal gate: every other gate can be built from NANDs
NOR	all inputs are 0	Also universal; used in latches
XOR	the inputs differ	Adders, parity, comparing two bits

• Relay and PLC logic is the same. Contacts in series are an AND, contacts in parallel are an OR, a normally-closed contact is a NOT: see Ladder Logic in Practice.
• Open-drain and open-collector outputs can only pull low; several can share one line (a wired-AND) with a pull-up resistor, as in I2C.
• Schmitt-trigger inputs (74HC14, 74HC132) have two thresholds, so a slow or noisy signal gives a clean output.

Boolean algebra and De Morgan

Rule	Expression	Use
Identity and null	A · 1 = A; A · 0 = 0; A + 0 = A; A + 1 = 1	Simplify when an input is fixed
Complement	A · A̅ = 0; A + A̅ = 1	A signal and its inverse
Distributive	A · (B + C) = A · B + A · C	Factor and expand
Absorption	A + A · B = A	Drop redundant terms
De Morgan	(A · B)̅ = A̅ + B̅; (A + B)̅ = A̅ · B̅	Convert AND to OR with inversions; build any function from NANDs

To simplify a function, write its truth table, then group the 1s in a Karnaugh map or apply the rules above. Fewer gates mean less cost and delay; but clear logic is worth more than the last gate, and a programmable device (PLD, FPGA) or a few lines of code can replace a handful of gates.

Logic families and levels

Gates come in families that differ in supply voltage, speed, power and the voltages they treat as 0 and 1. The 74-series numbering stays the same (7400 is four NAND gates), with letters for the technology: LS (old bipolar TTL), HC (fast CMOS), HCT (CMOS with TTL-compatible inputs), LVC and AHC (low-voltage CMOS), and the 4000 series (slow CMOS with a wide supply range, 3–15 V).

Family	Supply	VIH min	VIL max	VOH min	VOL max	High noise margin	Low noise margin
LS TTL	5.0 V	2.00 V	0.80 V	2.70 V	0.50 V	0.70 V	0.30 V
74HC (5 V)	5.0 V	3.50 V	1.50 V	4.40 V	0.33 V	0.90 V	1.17 V
74HCT (5 V)	5.0 V	2.00 V	0.80 V	4.40 V	0.33 V	2.40 V	0.47 V
74LVC (3.3 V)	3.3 V	2.00 V	0.80 V	2.20 V	0.55 V	0.20 V	0.25 V

The noise margin is how much noise a signal can have and still be read correctly: the high margin is V_OH − V_IH, the low margin is V_IL − V_OL. An LS TTL gate driving another has margins of only 0.7 V and 0.3 V, a CMOS gate has more than 0.9 V and 1.1 V: another reason CMOS dominates.

Driver → receiver	Works?	Notes
3.3 V LVC → 5 V HCT	Yes	HCT’s VIH is 2.0 V, so 3.3 V is read as high
3.3 V → 5 V HC	No (marginal)	HC needs 3.5 V for a high at 5 V
5 V HC or HCT → 3.3 V LVC	Yes, if the 3.3 V input is 5 V tolerant	LVC inputs are 5 V tolerant; many MCU pins are not
5 V → 3.3 V MCU pin	Only with a divider or level shifter	See Microcontroller Electronics

• Unused inputs must be tied to 0 or 1 (a CMOS input floats and oscillates, drawing current).
• Outputs must not be connected together unless they are open-drain or tri-state types.
• Fan-out is how many inputs an output can drive: a CMOS input needs almost no DC current, so the limit is the capacitance (it slows the edges), typically a few tens of inputs.
• Decouple every chip with 100 nF at its supply pins (see Capacitors).

Combinational circuits: decoders, multiplexers and adders

A combinational circuit has no memory: its output depends only on its present inputs. The common building blocks are decoders, multiplexers and adders.

Block	Function	Example chip	Use
Decoder	N select lines turn on one of 2N outputs	74HC138 (3 to 8), 74HC154 (4 to 16)	Chip-select lines; driving one of many LEDs or relays
Encoder	The opposite: which of 2N inputs is active, as a binary number	74HC148 (priority encoder)	Keypads, interrupt priority
Multiplexer	Selects one of 2N inputs to one output	74HC151 (8:1), 74HC4051 (analog 8:1)	Reading many sensors with one ADC pin
Demultiplexer	Sends one input to one of 2N outputs	74HC138 used backwards	Routing signals
Comparator	Compares two binary numbers	74HC85	Thresholds in hardware
Adder	Adds two binary numbers	74HC283 (4 bit)	Arithmetic units
Tri-state buffer	Passes, or disconnects (high impedance)	74HC244, 74HC245	Shared buses

Latches, flip-flops and registers

To remember a bit, a circuit needs feedback. The simplest memory is an SR latch of two cross-coupled NOR (or NAND) gates: one input sets the output to 1, the other resets it to 0, and with both inactive it holds. A flip-flop adds a clock so that the state changes only at a defined instant.

Element	Behavior	Use
SR latch	Set and reset inputs; holds when both are inactive	Switch debounce, simple memory, alarms
D latch	Follows D while the enable is high; holds when low	Holding data on a bus
D flip-flop	Copies D to Q on the rising edge of the clock	The basic register bit; synchronizing an input
T flip-flop	Toggles on each clock when T = 1	Counters, divide by two
JK flip-flop	Set, reset, hold or toggle	General-purpose; rarely used now
Register	A row of D flip-flops sharing a clock	Holding a byte (74HC574, 74HC273)
Shift register	Data moves one place on each clock	Serial to parallel and the reverse (74HC595, 74HC165)

• Edge-triggered flip-flops change only at the clock edge, which makes large synchronous systems predictable.
• Asynchronous set and reset inputs force the state at once and bypass the clock: use them to initialize at power-up.
• Metastability. A signal that changes close to the clock edge (an external button, another clock domain) can put a flip-flop in an undefined state for a moment; pass it through two flip-flops in series to resolve it (a synchronizer).
• Power-up state of flip-flops is random: add a reset.

Counters and frequency division

A counter is a chain of flip-flops that counts clock pulses. In a ripple (asynchronous) counter each stage clocks the next, so each stage divides the frequency by two; in a synchronous counter all stages share the clock and change together, which avoids glitches and runs faster.

Counter	Sequence	Chip	Use
Binary	0 to 2n − 1, then back to 0	74HC161 (4 bit), 74HC4040 (12 bit ripple)	Frequency division, addresses
Decade (BCD)	0 to 9	74HC160, 74HC4017 (decade with 10 decoded outputs)	Counting in decimal; LED chasers
Up/down	Counts either way	74HC191	Position counting from an encoder
Johnson (twisted-ring)	A moving block of 1s	74HC4017	Sequencers

Timing: delay, setup, hold and clock speed

Signals take time to pass through gates. The propagation delay t_pd is the time from an input change to the output change (about 5–15 ns for 74HC at 5 V, 2–5 ns for LVC). A flip-flop needs its data stable for a setup time t_su before the clock edge and a hold time t_h after it; the output changes a clock-to-Q delay t_cq after the edge.

• Glitches. When several inputs change at once, a combinational output can flicker briefly; do not use it as a clock, and use synchronous design where you can.
• Clock distribution. A clock that reaches different chips at different times (skew) causes errors: keep the clock traces short and equal on fast boards.
• Switching noise. Fast edges draw spikes of current: decouple every chip and add series resistors (22–47 Ω) on long fast lines.

Using logic chips in practice

Job	Part	Notes
Level-shift or buffer a signal	74HC244/245, 74LVC1T45, 74AHCT125	Check the direction control and the speed
Clean a slow or noisy edge	74HC14 Schmitt inverter	Debounce with an RC (see Microcontroller Electronics)
Enable one chip of several	74HC138 decoder	Address decoding
Add outputs to a microcontroller	74HC595 shift register	Three pins control any number of outputs
Add inputs	74HC165 shift register	Reads a bank of switches
Combine a few signals	Single-gate chips (74LVC1G08)	One gate in a tiny package
Drive a load	ULN2803 (Darlington array), 74HC with a MOSFET	See Driving Motors and Actuators
Count or divide	74HC4040, 74HC4017	The CMOS 4000 series works from 3 to 15 V

Logic chips with a microcontroller

• SPI is a shift register. The 74HC595 and 74HC165 connect directly to a microcontroller’s SPI pins.
• Wired-AND buses and interrupts: several open-drain devices can share an interrupt line with one pull-up.
• Glue logic. A gate or two can combine chip-select and enable signals so that the microcontroller does not need extra pins.
• Use the microcontroller instead when the function is complex: software is cheaper than hardware, until speed or simultaneity demands logic.

Memory and programmable logic

Device	What it is	Use
ROM, EPROM, flash	Non-volatile memory, read (and rewritten slowly)	Programs and constants
SRAM	Fast volatile memory, a flip-flop per bit	Working memory, caches
DRAM	Dense volatile memory refreshed regularly	Large memories (PCs, boards with SDRAM)
EEPROM, FRAM	Small non-volatile memory with byte writes	Settings, calibration data
PLD (GAL, CPLD)	Programmable AND/OR logic arrays with flip-flops	Replace several chips of glue logic
FPGA	Thousands to millions of programmable gates and flip-flops, configured by a bitstream	Fast parallel processing, custom interfaces, prototyping chips
Microcontroller	A processor with memory and peripherals	Most control tasks

A memory with n address lines has 2ⁿ locations: 16 lines address 65 536 locations. Programmable logic is described in a hardware description language (VHDL or Verilog) or drawn as a schematic, compiled to a configuration file, and loaded into the chip. Ladder logic on a PLC is a software version of the same idea: see How PLCs Work.

Common faults

Symptom	Likely cause	Try
Output stuck high or low	Missing supply or ground, an input driven by nothing, outputs connected together	Check the supply pins; scope the inputs; look for two drivers on a line
Chip hot or the supply current high	A floating CMOS input, two outputs fighting, a short	Tie unused inputs; check for contention
Random or intermittent behavior	A floating input, no decoupling, noise on a clock or reset	Add pull-ups, 100 nF capacitors, a Schmitt input
Wrong value read from the other voltage family	Logic levels not compatible	Check VOH against VIH; use a level shifter or an HCT part
Counter skips or counts extra	Bounce or noise on the clock, a ripple counter being read while it changes	Debounce; use a synchronous counter; latch the value before reading
Shift register shows garbage	Wrong clock edge or bit order, a missing latch pulse, a chain too long for the clock	Check the datasheet timing and the order of bits; slow the clock
Works slowly but fails fast	Setup or hold violation, a long path, supply droop	Slow the clock; shorten the path; check the timing numbers
Glitches on an output	Several inputs changing at once into combinational logic	Register the output with a flip-flop; add a small filter if it is slow

Related

• Digital Electronics and Microcontrollers: the overview of this guide.
• Op-amps and Integrated Circuits: comparators, the 555 timer and basic logic chips.
• Microcontroller Electronics: connecting logic chips to a microcontroller.
• Transistors: the switches inside every gate.
• Embedded Systems and PLC & Logic Control: logic in software.
• Bitwise and Register Field Calculator.

FAQ

What is the difference between a latch and a flip-flop?

A latch is transparent while its enable is active and holds when it is not. A flip-flop samples its input only at the clock edge, so its output changes at one defined instant.

Why does a floating CMOS input cause trouble?

It has an enormous resistance, so it picks up noise and drifts through the region where both transistors conduct, drawing current and giving random outputs. Tie unused inputs high or low.

Can I connect a 5 V HC output to a 3.3 V input?

Only if the 3.3 V input is 5 V tolerant. Otherwise use a divider (for slow signals), a level shifter or an LVC buffer powered from 3.3 V.

How do I debounce a switch with logic?

Use an SR latch (two NAND gates) with a changeover switch, a Schmitt-trigger inverter after an RC filter, or a debounce chip. In software, ignore changes for 10–20 ms.

Should I use logic chips or a microcontroller?

A microcontroller for anything with decisions and sequences. Logic chips for fast, simple or parallel jobs, to add pins, to shift levels or to glue chips together, and where a program is not wanted.

References

• Texas Instruments and Nexperia, 74HC/HCT/LVC logic family datasheets and the Logic Guide; onsemi and Texas Instruments 4000-series datasheets.
• Horowitz, P. and Hill, W., The Art of Electronics, 3rd ed., Cambridge University Press: chapters on digital electronics and logic families.
• Wakerly, J. F., Digital Design: Principles and Practices, Pearson.
• IEEE 91 / IEC 60617, Graphical symbols for logic functions.

Last reviewed: October 2026. Values are typical: check the datasheets of the parts you use.