Design Workflow: Schematic to Board
The steps from requirements to files, schematic practice, footprints, rules, versions and how big the board will be.
The steps, and what each produces
A good board follows a fixed order. Each step ends with something you can check, and a problem found early costs minutes where the same problem found on a built board costs weeks.
| Step | Produces | Check |
|---|---|---|
| 1. Requirements | List of voltages, currents, signals, size, environment, cost, quantity | Can someone else read it and agree? |
| 2. Schematic | Circuit with part values, net names, notes | Electrical rules check (ERC) clean; peer review |
| 3. Footprints and library | A land pattern for every part, 3D model, correct pin numbers | Print 1:1 and lay the real part on it |
| 4. Rules and outline | Stack-up, trace and space rules, via sizes, board shape, mounting holes | Match your fabricator’s capabilities |
| 5. Placement | Parts in their zones, connectors on edges | Review before routing (see Component Placement and Floorplanning) |
| 6. Routing | Traces and vias, planes poured | Design rules check (DRC) clean (see Routing, Vias and Return Paths) |
| 7. Review | Checklist signed off | A second pair of eyes (see Manufacturing Rules, Files and Design Review) |
| 8. Files | Gerber, drill, BOM, pick-and-place, assembly drawing | Open the Gerbers in a viewer and compare with the design |
Requirements: write them down first
Most layout problems are really requirement problems that surface late. Before you open the schematic editor, write down:
- Power: input voltage range, each rail’s voltage and maximum current, and any battery or hot-plug behavior.
- Signals: the fastest edge, the highest frequency, any interfaces with impedance rules (USB, Ethernet, DDR, RF) and analog inputs that need quiet ground.
- Mechanical: board size and shape, enclosure, connector positions, mounting holes, height limits.
- Environment: temperature range, humidity, vibration, exposure to voltage above 50 V, and the standards you must pass (EMC, safety).
- Production: quantity, assembly method (hand, paste and oven, a service), test strategy and cost target.
Schematic practice
- Draw for the reader: signal flow left to right, power at the top, ground at the bottom, one function per block.
- Name every net that matters (3V3, SDA, MOTOR_EN), and use power symbols, not wires across the page.
- Put the part number and the value on the schematic, so that the bill of materials is generated, not typed.
- Add decoupling capacitors to the schematic, one per supply pin, so that they are not forgotten (see Power, Ground and Decoupling).
- Add test points on every rail and key signal, plus a place to attach a scope ground.
- Run the ERC and fix or explain every warning: unconnected pins, two outputs on a net and a missing power flag are real mistakes.
- Note the unusual: why a resistor is 4.7 kΩ, which parts are fitted only on a variant, any polarity.
Footprints: the commonest cause of a dead board
A footprint (land pattern) is the copper pattern, mask opening and silkscreen outline that a part solders to. A library footprint with a wrong pin number, a mirrored pad row or a wrong pitch cannot be fixed on the finished board except by wires. Every footprint must be checked against the manufacturer’s data sheet drawing, not against another footprint of the same name.
- Print the layout at 1:1 on paper and lay the real parts on it before you order boards. It catches pitch, size and orientation errors in a minute.
- Check pin 1 and the pin order for every IC, connector and polarized part, including which side of the board a connector is seen from.
- Check the pad size against IPC-7351 or the data sheet recommendation (see Soldering for hand-solderable pads: extend pads 0.5 to 1 mm beyond the part).
- Include a courtyard (the keep-out around a part) so that the design-rule check catches parts that are too close.
- Keep one library with checked parts and a record of who checked them.
Design rules, outline and layers
Set the rules in the layout tool before routing, so that the program stops you from breaking them. The values below are a safe starting point for a low-cost prototype service; replace them with your fabricator’s published capabilities (see Manufacturing Rules, Files and Design Review).
| Rule | Starting value | Why |
|---|---|---|
| Trace width and spacing (signals) | 0.20 mm / 0.20 mm (8 mil) | Comfortably above the 0.127 mm (5 mil) minimum; better yield |
| Power traces | size for current (see Traces, Current, Spacing and Clearance) | Temperature rise and voltage drop |
| Via drill / pad | 0.3 mm / 0.6 mm | Standard through via; low-cost |
| Annular ring | 0.15 mm or more | Drill wander will not break the pad |
| Copper to board edge | 0.3 mm or more (0.5 mm preferred) | Router tolerance, no exposed copper |
| Hole to hole | 0.5 mm or more | Drilling and plating |
| Solder mask expansion | 0.05 mm | Mask registration |
| Silkscreen text | 1 mm high, 0.15 mm line | Legible after printing |
| Mounting holes | M3 holes (3.2 mm), at least 3 mm from the edge, keep-out for the screw head | Fit in the enclosure |
The board outline is a closed shape on its own layer; add small corner radii (1 to 2 mm) and mounting holes. Choose the layer count at this stage too (see Layer Stack-up and Impedance): adding a layer later means re-doing the routing.
How big will the board be?
Before placing anything, estimate the board area from the parts. Add up the courtyard areas and multiply by a factor for routing space, connectors and clearance: about 2 to 3 for a hand-routed two-layer board, 1.5 to 2 for a dense four-layer board.
Worked example: size of the sensor board
The example used through this guide is a USB-powered sensor board with a microcontroller, a 3.3 V regulator, an I2C sensor, two LEDs, a button and two headers (see Worked Layouts).
| Part | Qty | Courtyard | Total area |
|---|---|---|---|
| Microcontroller, TQFP-32 | 1 | 9.5 × 9.5 mm | 90 mm² |
| LDO regulator, SOT-223 | 1 | 9.0 × 7.5 mm | 68 mm² |
| USB-C receptacle (16 pin) | 1 | 10.0 × 8.0 mm | 80 mm² |
| I2C sensor, 3 × 3 mm LGA | 1 | 4.5 × 4.5 mm | 20 mm² |
| TVS diode, SOT-23 | 1 | 4.0 × 3.6 mm | 14 mm² |
| Crystal, 3.2 × 2.5 mm | 1 | 4.2 × 3.5 mm | 15 mm² |
| Resistors and capacitors, 0603 | 22 | 2.8 × 1.6 mm | 99 mm² |
| Bulk capacitors, 0805 | 3 | 3.4 × 2.2 mm | 22 mm² |
| LEDs, 0603 | 2 | 2.8 × 1.6 mm | 9 mm² |
| Pin headers, 1 × 6, 2.54 mm | 2 | 16.0 × 3.4 mm | 109 mm² |
| Tactile switch, 6 mm | 1 | 7.0 × 7.0 mm | 49 mm² |
- The courtyards add up to 575 mm² for 36 parts and 137 pins.
- With a factor of 2.3 the board area is 575 × 2.3 = 1 322 mm². At a 4:3 shape that is about 42 × 31 mm; rounding to 5 mm steps gives 45 × 30 mm = 1 350 mm².
- Parts then cover 43 % of the board, which is a comfortable density for hand assembly.
- Pin density: 137 pins on 13.5 cm² is 10 pins/cm². As a rough guide, below about 20 pins/cm² two layers are easy, 20 to 50 pins/cm² need care or four layers, and above that four or more layers are normal. This board passes with two layers if ground is kept as a pour (the guide is a heuristic, not a rule).
Worked example: is there room to route?
- Nets ≈ pins ÷ 2.4 (most nets join two or three pins) = 57. Average net length ≈ 0.35 × √area = 13 mm, so the total trace length is about 733 mm.
- On two layers with a 0.3 mm pitch (0.15 mm trace and 0.15 mm space) the area over both layers is 2 × 1 350 = 2 700 mm². The trace density is 733 ÷ 2 700 = 0.27 mm of trace per mm².
- A track at 0.3 mm pitch could fill up to 3.3 mm of trace per mm², but a realistic limit is about 35 % of that, 1.17 mm/mm². Usage is 23 % of the realistic limit: easy to route. Over about 60 % is the time to add a layer.
Why checks are worth their time
The cost of fixing an error rises steeply as the design moves toward production. This is the “rule of ten” (an estimate, not a measurement):
| Where the error is found | Relative cost to fix |
|---|---|
| Schematic | about 1× |
| Layout | about 10× |
| Prototype boards | about 100× |
| Production | about 1 000× |
Worked example: time budget for a small board
- A first-time designer might spend 4 h on requirements and part selection, 6 h on schematic and review, 4 h on footprints and library check, 4 h on placement, 8 h on routing, 4 h on DRC, review and files: a total of 30 hours.
- Review and checks (schematic review, footprint check, DRC, final review) take about 27 % of that and prevent most respins. A respin costs the fabrication, a new round of assembly and at least a week of delay.
Design tools and version control
- Free tools: KiCad (full-featured, open source), EasyEDA (browser-based with a manufacturing link), Autodesk Fusion (electronics included, free for hobbyists with limits) and LibrePCB. Professional tools such as Altium Designer, Cadence Allegro and OrCAD add team features and advanced signal integrity.
- Version control: keep the project in Git (KiCad’s text files diff well) or at least a dated folder for every release. Tag the revision that went to the fabricator, and write the revision on the silkscreen.
- Revision name on the board: a letter and date on the silkscreen (for example “SB-01 rev B 2026-11”) so you can tell the boards apart.
- Back up: a project that exists in one place does not exist.
Troubleshooting
| Symptom | Likely cause | What to do |
|---|---|---|
| Part does not fit its pads | Wrong footprint or pitch | Check against the data sheet; print 1:1 before ordering |
| Part works mirrored or rotated | Pin 1 or a connector seen from the wrong side | Check orientation marks; compare the 3D view |
| DRC reports hundreds of errors | Rules set after routing, or the wrong rule set | Set the rules first; use the fabricator’s rules |
| Board too large or too crowded | No area estimate at the start | Estimate the area from the courtyards; consider more layers |
| Nets unconnected in the layout | Schematic not updated, or footprint pins unassigned | Update the PCB from the schematic; fix ERC warnings |
| Cannot find what changed | No version control | Git or dated folders from the start |
Related
- PCB Design and Layout: the overview of this guide.
- Layer Stack-up and Impedance: choosing the layers.
- Component Placement and Floorplanning: the next step.
- PCB Prototyping: ordering the boards.
FAQ
What is the first step in designing a PCB?
Write down the requirements: voltages, currents, fastest signals, board size, environment and quantity. Everything else depends on them.
What is the difference between ERC and DRC?
The electrical rules check (ERC) tests the schematic for errors such as unconnected pins; the design rules check (DRC) tests the layout against manufacturing rules such as spacing and drill size.
Why check footprints against the data sheet?
A footprint error cannot be fixed on the finished board. Library footprints are sometimes wrong: print the layout at 1:1 and lay the real parts on it.
How do I estimate the board size?
Add up the courtyard areas of all parts and multiply by 2 to 3 for a two-layer board or 1.5 to 2 for a dense four-layer board.
Which free PCB software should I use?
KiCad is the most capable free tool and works for professional boards; EasyEDA is the simplest if you also order through its linked service.
References
- IPC-2221B, Generic Standard on Printed Board Design; IPC-7351B (land patterns).
- Montrose, M. I., Printed Circuit Board Design Techniques for EMC Compliance, IEEE Press.
- KiCad documentation (kicad.org); fabricator capability pages.
Last reviewed: October 2026. Rules of thumb for area, density and cost are estimates: confirm with your tools and fabricator.