Power, Ground and Decoupling

Power distribution, plane resistance, target impedance, capacitor choice and placement, switching loops and grounding.

On this page

Power distribution: a tree, not a loop
Resistance and drop in traces and planes
Decoupling: the target impedance method
Choosing the capacitors
Placing and connecting decoupling capacitors
Ground bounce
Switching regulators: the hot loop
Filtering power for sensitive circuits
Grounding: one plane
Troubleshooting
FAQ

Power distribution: a tree, not a loop

Power comes in at a connector, passes through protection and regulation, and is delivered to each part. Draw it as a tree: the highest-current branches are the shortest and widest, and the sensitive loads sit at the end of their own branch where they are not affected by the current of the others.

Bulk capacitor at the entry (10 to 100 µF) to hold the input steady and to absorb the inrush.
Regulator close to the load it serves, or close to the entry with a wide route; keep the high-current loop of a switching regulator small (below).
Separate branches for noisy loads (motors, relays, LEDs, radio) and for quiet analog circuits; join them only at the entry.
Power and ground planes (on a four-layer board) spread the current and give a very low impedance: give each rail its own area on one power layer.
Protect the input: a fuse or a PTC, a reverse-polarity MOSFET or diode and a TVS diode (see Electronics Fundamentals).

Resistance and drop in traces and planes

A square of 1 oz copper has a resistance of 0.49 mΩ regardless of its size (see Traces, Current, Spacing and Clearance). The resistance of a pour or plane is the sheet resistance times the number of squares along the current path.

Worked example: a power pour

A pour 50 mm long and 10 mm wide is 5 squares: R = 5 × 0.49 = 2.5 mΩ. At 3 A the drop is 7.4 mV.
If the pour is squeezed to 2 mm at a neck, that part is 25 squares and the drop becomes 36.9 mV: the narrowest point dominates.
Planes are far better: a 40 × 30 mm solid plane carrying current from one side to the other is only 0.75 squares, R = 0.75 × 0.49 = 0.37 mΩ for a 1 oz layer.

Decoupling: the target impedance method

A digital chip draws current in short pulses at the clock rate. The supply wiring has resistance and inductance, so the voltage at the chip dips with each pulse unless something nearby supplies the charge. That “something” is the decoupling (bypass) capacitor. The target impedance method sets how low the impedance of the power network must be, over the frequency range of the pulses, for the ripple to stay within the allowed limit.

Z_target = V_supply × ripple ÷ ΔI

Worked example: a 3.3 V microcontroller rail

The chip may draw a step of 0.5 A. Allow 5 % ripple: 0.165 V.
Z_target = 3.30 × 0.05 ÷ 0.5 = 0.33 Ω, from DC up to the frequency where the chip’s own package and on-chip capacitance take over (typically 50 to 100 MHz).
The regulator handles the low frequencies (up to about 100 kHz); the bulk capacitors the middle; and the 100 nF capacitors close to the pins the high ones. The curves of three mounting inductances are shown below.

Impedance of a 100 nF capacitor with different mounting inductance, against the target.

Choosing the capacitors

A real capacitor has equivalent series resistance (ESR) and inductance (ESL), so it behaves as a capacitor below its self-resonant frequency (SRF = 1 ÷ 2π√(LC)) and as an inductor above it. The inductance of its mounting (pads, vias and traces) adds to the ESL and is usually larger than the capacitor’s own.

Capacitor	SRF with 1 nH	with 2 nH	with 5 nH
10 µF (0805)	1.6 MHz	1.1 MHz	0.7 MHz
1 µF (0603)	5.0 MHz	3.6 MHz	2.3 MHz
100 nF (0402)	15.9 MHz	11.3 MHz	7.1 MHz
10 nF (0402)	50.3 MHz	35.6 MHz	22.5 MHz

Use ceramic (X7R or X5R) capacitors for decoupling, in 0402 or 0603 packages: the smaller the package, the lower the ESL. Check the DC-bias derating: a 10 µF 6.3 V X5R can lose half of its capacitance at 3.3 V.
One 100 nF per supply pin, plus a 1 to 10 µF per supply rail near the chip and a bulk 10 to 47 µF near the regulator.
Do not mix many values hoping for broad coverage: between two capacitors of different values a parallel resonance (anti-resonance) can form. Use the same value in parallel, and lower the inductance of the mounting.
Electrolytic and tantalum capacitors have high ESR and ESL: good for bulk storage, not for high-frequency decoupling.
Follow the data sheet of the chip: it often gives capacitor values for its analog and PLL supply pins.

Worked example: how many 100 nF capacitors at 50 MHz?

At 50 MHz a 100 nF capacitor with ESR 20 mΩ and a mounting inductance of 2 nH has an impedance of 0.60 Ω (mostly inductive). The target is 0.33 Ω, so 2 capacitors in parallel are needed (impedances in parallel divide).
If the same capacitor is 10 mm away (10 nH): 3.11 Ω, and 10 of them are needed. Placement is worth five times the capacitors.

Mounting	Impedance of one 100 nF at 50 MHz	Number for 0.33 Ω
beside the pin, 2 nH	0.60 Ω	2
a short stub, 5 nH	1.54 Ω	5
10 mm away, 10 nH	3.11 Ω	10

Worked example: charge for a burst

A block of logic switches and draws 50 mA for 10 ns. How much capacitance keeps the rail from dipping by more than 50 mV? C = ΔI Δt ÷ ΔV = 0.05 × 10×10⁻⁹ ÷ 0.05 = 10 nF.
One 100 nF capacitor is ten times what the burst needs, if it can deliver its charge within 10 ns: it can only if its inductance is small (a time constant √(LC) of a 2 nH + 100 nF pair is about 14 ns): that is why 10 nF at the pin is better than 100 nF far away.

Placing and connecting decoupling capacitors

Good and bad decoupling capacitor placement.

The capacitor goes between the supply pin and the ground pin, as a tiny loop. Put it on the same side as the chip, with the pad touching or almost touching the pin.
Route the supply to the capacitor first, then to the pin (the current passes through the capacitor), or place the capacitor so that the short trace ends on the pin.
Via to the ground plane right at the capacitor’s ground pad, and a via to the power plane at the supply pad; two vias per pad for the larger capacitors.
Do not share a via between several capacitors and do not connect through a long, thin trace: a trace of 10 mm is 10 nH.
On a two-layer board, run the ground side as a short, wide trace to the ground pour.
Under BGAs, put capacitors on the back, directly under the part, with vias in the BGA fan-out.

Ground bounce

When several outputs switch at once, the current surge through the ground connection’s inductance lifts the chip’s ground above the board ground for a moment: ground bounce, V = L × di/dt.

Worked example: eight outputs switching

8 outputs each switch 20 mA in 2 ns: di/dt = 8 × 0.02 ÷ 2 ns = 0.08 A/ns.
With 2 nH in the ground return (a short trace and a via) the bounce is 0.16 V. With 10 nH (a 10 mm trace) it is 0.80 V: enough to disturb a 3.3 V logic input (a margin of 0.4 V).
The cures: lower inductance (planes, short vias), fewer outputs switching together, slower edges (series resistors) and local decoupling.

Switching regulators: the hot loop

A buck converter chops the input at hundreds of kHz with edges of a few nanoseconds. The pulsed current flows in the hot loop: input capacitor, high-side switch, low-side switch (or diode) and back to the capacitor. Keep this loop as small as possible; it is the source of most of the noise, and it is set by placement.

Worked example: the voltage spike of the hot loop

The switch turns off 2.0 A in 5 ns: di/dt = 0.40 A/ns.
With a hot-loop inductance of 2 nH (the input capacitor right beside the switch) the spike is L × di/dt = 0.80 V. With 10 nH (a 10 mm loop) it is 4.0 V, enough to exceed the rating of the switch and to radiate.
A loop of 20 mm of trace is about 20 nH: so keep the capacitor within 2 to 3 mm of the converter pins.

Input capacitor directly across the VIN and PGND pins; a second ceramic of 100 nF as close as possible.
Switch node (SW): keep the copper small and away from sensitive traces; do not put a ground pour under the inductor’s switching pad if the data sheet says not to.
Inductor beside the SW pin, feedback trace away from the inductor and the SW node, taken from the output capacitor.
Ground: a solid ground plane directly under the converter, with the PGND pins connected by vias right at the pads.
Follow the data sheet’s layout example: it is the tested one.

Filtering power for sensitive circuits

A sensitive analog circuit (an ADC reference, an audio amplifier, a radio) may need cleaner power than the board’s main rail. Two common ways are a ferrite bead or an LC filter and a low-noise regulator.

Worked example: an LC filter and a ferrite bead

L = 1 µH and C = 10 µF: f₀ = 1 ÷ (2π√(LC)) = 50.3 kHz, a characteristic impedance √(L ÷ C) = 0.32 Ω. Above f₀ the filter attenuates at 40 dB per decade, but it rings at f₀ unless damped: add a series resistance of about 0.32 Ω, or an electrolytic of ESR close to that.
A ferrite bead of 120 Ω at 100 MHz in series with the supply and a 10 µF capacitor (ESL 2 nH, impedance 1.26 Ω at 100 MHz) forms a divider: attenuation at 100 MHz = 20 log₁₀(1.26 ÷ 120) = -40 dB. At low frequency the bead is almost a short, so it filters only the high-frequency noise.
Check the DC drop of the bead (its resistance is 20 to 100 mΩ) and its current rating.

Grounding: one plane

Use a single, solid ground plane (a layer on a four-layer board, a pour on a two-layer board). The old advice of separate analog and digital grounds usually makes the problem worse (see Routing, Vias and Return Paths): put the analog circuits in their own area and keep the digital currents out of it by placement.
Star points are for high-current wiring (a motor supply, a battery): join the power ground and the signal ground at one place.
Connect shield and chassis ground through a 1 MΩ resistor and a 10 nF capacitor in parallel, or as the product standard requires.
Avoid ground loops through cables: one ground connection between boards, close to the signals.

Troubleshooting

Symptom	Likely cause	What to do
Resets under load or when outputs switch	Supply sag or ground bounce	Add decoupling at the pins; widen supply; slow edges
ADC readings noisy	Digital noise on the analog supply	Filter the analog supply; move the noisy parts; solid ground
Regulator oscillates or gets hot	Wrong output capacitor ESR, long traces	Follow the data sheet; add the specified capacitor close by
Switching noise at the output	Large hot loop; poor input capacitor	Shrink the loop; add a 100 nF at the pins
Capacitor value not what is on the label	DC-bias derating of ceramic	Use a higher voltage rating or a larger package
EMC test fails around the regulator frequency	Hot loop and switch node radiate	Reduce the loop area; add a snubber; shield

PCB Design and Layout: the overview of this guide.
Traces, Current, Spacing and Clearance: trace widths and drops.
Signal Integrity and EMC: EMC and noise.
Electronics Fundamentals and the Electronics tools.

FAQ

How many decoupling capacitors do I need?

One 100 nF per supply pin, close to the pin, plus a larger one (1 to 10 µF) per rail near the chip and bulk capacitance at the regulator.

Why are decoupling capacitors placed so close?

Each millimeter of trace adds about 1 nH of inductance, which blocks the capacitor’s help at high frequency: 10 nH has an impedance of over 3 Ω at 50 MHz.

Should I split the ground plane for analog and digital?

No: use one solid plane and keep the analog and digital parts in separate areas. Splits cause return-path breaks.

What is ground bounce?

A voltage spike on the chip’s ground caused by the inductance of the return path when many outputs switch together (V = L di/dt).

Where do I put the switching regulator’s input capacitor?

Within a few millimeters of the VIN and ground pins: it carries the pulsed current of the hot loop.

References

Bogatin, E., Signal and Power Integrity: Simplified, Prentice Hall (target impedance, decoupling).
Ott, H. W., Electromagnetic Compatibility Engineering, Wiley; Texas Instruments, Practical Guidelines to Designing an EMI-Compliant PCB (application note).
Murata and TDK ceramic capacitor tools (DC bias and impedance data); regulator data sheet layout guidelines.

Last reviewed: October 2026. Capacitor, mounting and loop inductances are typical: simulate or measure for critical designs.