Signal Integrity and EMC
When a trace is a transmission line, termination, crosstalk, high-speed rules, radiated emissions and ESD.
When does a trace become a transmission line?
A signal takes time to travel along a trace, about 6.0 ps per millimeter on an FR-4 board (152 ps per inch). If the signal changes slowly compared with this delay, the whole trace is at one voltage and behaves as a simple wire. If the edge is fast, the trace is a transmission line with its own impedance, and a signal that meets a mismatch reflects, rings and overshoots. The usual rule: treat the trace as a transmission line when its length is more than about one sixth of the length of the signal edge (edge length = rise time ÷ delay per unit length).
What counts is the edge, not the clock frequency: a 1 MHz clock with a 1 ns edge needs the same care as a 100 MHz clock with a 1 ns edge. The significant frequency content of an edge extends to the “knee” at 0.35 ÷ tr.
| Logic | Rise time | Knee frequency | Edge length | Critical trace length |
|---|---|---|---|---|
| 74HC logic | 10 000 ps | 35 MHz | 1 668 mm | 278 mm |
| Fast CMOS, 3.3 V LVC | 2 000 ps | 175 MHz | 334 mm | 56 mm |
| Fast SPI / microcontroller GPIO | 1 000 ps | 350 MHz | 167 mm | 28 mm |
| USB 2.0 high speed | 500 ps | 700 MHz | 83 mm | 14 mm |
| LVDS, USB 3 | 100 ps | 3 500 MHz | 17 mm | 3 mm |
Worked example: a 1 ns GPIO edge
- Delay on the four-layer microstrip: 6.0 ps/mm. A 1 000 ps edge spans 1 000 ÷ 6.0 = 167 mm of trace.
- One sixth of that is 28 mm: any trace longer than about 28 mm needs to be treated as a transmission line (matched, kept over a ground plane, no stubs). Shorter traces are “electrically small”.
- Most microcontroller boards are mostly electrically small for their GPIOs but not for clock, USB and memory buses. A 10 ns 74HC edge only needs care at 280 mm.
- The knee frequency is 0.35 ÷ 1 ns = 350 MHz: the board must work (and pass EMC tests) up to those frequencies even if the clock is 8 MHz.
Reflections and termination
When a signal meets a change of impedance it partly reflects: the reflection coefficient is Γ = (ZL − Z0) ÷ (ZL + Z0), and the voltage at the receiver is the incident wave plus the reflected one.
| Load on a 50 Ω line | Γ | Peak voltage at the load for a 3.3 V step |
|---|---|---|
| Open (CMOS input) | 1.00 | 6.60 V |
| 100 Ω | 0.33 | 4.40 V |
| 50 Ω (matched) | 0.00 | 3.30 V |
| 25 Ω | -0.33 | 2.20 V |
| Short | -1.00 | 0.00 V |
An open (high-impedance CMOS) input reflects everything, so the first edge arrives at nearly twice its size: 6.6 V on a 3.3 V logic, above the absolute maximum rating of most chips. The reflection returns to the driver, reflects again and the line rings. A matched termination absorbs the wave.
Worked example: series termination
- A driver with output resistance 20 Ω drives a 50 Ω line. Add a series resistor Rs = Z0 − Rdrv = 50 − 20 = 30 Ω (use 33 Ω) at the driver, so that the source matches the line.
- The step is launched at half amplitude, reaches the open end, doubles to full and the reflection returns to the matched source and is absorbed. No ringing; no DC power. The receiver sees the full edge after the line delay.
- With a driver of 35 Ω the resistor would be 15 Ω (use 15 Ω). The data sheet or an IBIS model gives the driver resistance.
- The cost: the resistor and the input capacitance (5 pF) form an RC delay of 165 ps: negligible at 1 ns edges.
- Parallel termination (50 Ω to ground at the end) works too, but it draws power: 3.3 V on 50 Ω is 66 mA, about 109 mW at 50 % duty, which is why series termination is preferred for point-to-point CMOS.
- Series termination at the driver: point-to-point CMOS signals and clocks.
- Parallel (far-end) termination: multi-drop buses and fast differential links (100 Ω across a pair).
- AC termination (a resistor and a capacitor in series): parallel termination without DC power.
- Place the termination next to the pin it serves, with the shortest possible stub.
Crosstalk
A fast edge on one trace induces a small signal on its neighbor through the mutual capacitance and inductance of the pair. The closer the traces and the longer they run in parallel, the larger the effect, and the nearer the ground plane (small h), the smaller it is.
| Spacing | Relative crosstalk (model) | In dB |
|---|---|---|
| 1 × h (0.21 mm) | 50 % | -6.0 dB |
| 2 × h (0.42 mm) | 20 % | -14.0 dB |
| 3 × h (0.63 mm) | 10 % | -20.0 dB |
| 5 × h (1.05 mm) | 4 % | -28.3 dB |
Worked example: the “3W rule”
- A trace of w = 0.35 mm is 0.21 mm above the plane. At a spacing of the trace width, s = 0.35 mm (s ÷ h = 1.7), the relative coupling is 1 ÷ (1 + 2.8) = 26 %.
- At a center-to-center spacing of 3 w, the edge-to-edge spacing is 2 w = 0.70 mm (s ÷ h = 3.3): 8 %. That is a 3.2× reduction: the origin of the “3W” rule (keep clock and sensitive traces at least 3 trace widths apart).
- The best fix is to keep the plane close: halving h cuts the coupling by about four. The model is a rule of thumb: coupling also depends on length and edge rate.
- Separate clocks, resets and sensitive analog traces from fast and high-current ones; give them a ground trace guard only if it is stitched at both ends and at every few millimeters.
- Cross, not run parallel: on different layers, route at right angles.
- Keep parallel runs short.
Differential pairs and fast interfaces
Fast links (USB, Ethernet, HDMI, LVDS, CAN) send the signal as the difference of two traces. Noise that couples equally onto both cancels in the receiver, and the pair radiates little because the currents are opposite. The rules for a good pair:
- Impedance: 90 Ω differential for USB, 100 Ω for Ethernet and LVDS (see Layer Stack-up and Impedance).
- Constant spacing and symmetry along the whole route, and equal length (see Routing, Vias and Return Paths).
- Over an unbroken plane, with stitching vias next to each layer change.
- ESD and common-mode parts (TVS arrays, a common-mode choke) next to the connector, before any other part.
- USB 2.0 full speed (12 Mbit/s) is forgiving; high speed (480 Mbit/s) needs controlled impedance and short pairs; 5 Gb/s and above need a proper design.
- Follow the interface’s layout guide (USB-IF, the chip maker): it gives the numbers.
EMC: why boards radiate
Electromagnetic compatibility means a product neither emits more than the legal limits nor is upset by outside fields. Two mechanisms account for nearly all board emissions: differential-mode radiation from small current loops, and common-mode radiation from currents that flow on cables.
E ≈ 2.63 × 10−14 × f² × A × I ÷ r
Worked example: a loop and its limit
- A clock harmonic of 10 mA at 100 MHz flows in a loop of 400 mm² (4 cm²). At 3 m the field is 50.9 dBµV/m (351 µV/m).
- The FCC Class B limit at 3 m from 88 to 216 MHz is 43.5 dBµV/m: this loop is 7.4 dB over the limit (one harmonic, estimate).
- Reducing the loop area by 4 (a closer plane, a shorter route) gives 38.9 dBµV/m: 12 dB lower, so the harmonic is under the limit. Because the field goes as f², the 100 MHz harmonic radiates 100 times more than the 10 MHz one for the same current: it is the high harmonics (fast edges) that cause test failures. A series resistor that slows the edge cuts them.
- Slow the edges to what the circuit needs: a series resistor of 22 to 100 Ω on clocks and fast outputs; use the lowest drive strength.
- Keep loops small: solid return plane, decoupling at the pins, no slots (see Routing, Vias and Return Paths).
- Spread-spectrum clocking lowers the peak by spreading it over a band (3 to 10 dB).
- Guard the board’s edges: fence vias, ground pour and a ground ring for fast boards.
- Do not put fast signals on the edge or near connectors, where the field couples to the cable.
Cables and common-mode current
A cable is a far more efficient antenna than the board. A small unwanted common-mode current (the same direction on all conductors, returning through the air) on a cable of length L radiates a field E ≈ 1.257×10−6 f L Icm ÷ r (V/m; f in Hz, L in m, I in A, r in m).
Worked example: how little current is too much?
- A 1 m cable carries 5 µA of common-mode current at 50 MHz. At 3 m: E = 1.257×10−6 × 50×106 × 1 × 5×10−6 ÷ 3 = 105 µV/m = 40.4 dBµV/m.
- The FCC Class B limit in this band (30 to 88 MHz at 3 m) is 40 dBµV/m. So just 4.8 µA of common-mode current on a one-meter cable is the whole limit.
- That is why a few millivolts of ground-plane noise at the cable connector can fail a test: the noise voltage drives the cable shield or the pair. The fixes are at the connector: keep the connector at the same ground, filter the lines (ferrite bead, common-mode choke), bond the shield 360° to the chassis and keep clock traces away from the connector.
- Place connectors together at one edge, so that noise does not travel across the board to reach a cable.
- Filter every line that leaves the board at the connector: a ferrite bead or common-mode choke, plus a small capacitor to ground.
- Shielded cables: connect the shield to chassis at the connector with a short path, not through a pigtail.
- Ferrite clamps on cables are a quick fix, not a design.
ESD protection
A person can carry thousands of volts and discharge into a connector or a button (IEC 61000-4-2 uses 4 to 8 kV contact discharge, 8 to 15 kV in air). The peak current is about 7.5 A per kilovolt, with a rise time under a nanosecond. The protection is a TVS diode to ground at every exposed line, right at the connector.
Worked example: why the TVS must be next to the connector
- An 8 kV contact discharge gives a peak current of about 7.5 × 8 = 60 A with a rise of about 0.8 ns: di/dt = 75 A/ns.
- A TVS with a breakdown of 6 V and a dynamic resistance of 0.3 Ω clamps at about 6 + 60 × 0.3 = 24 V.
- The trace between the connector and the TVS has an inductance of about 1 nH per mm. With a 10 mm trace (10 nH) the inductive spike is L × di/dt = 750 V on top of the clamp, far beyond a 3.6 V chip’s limit. With a 2 mm trace (2 nH) it is 150 V.
- So: the TVS goes directly on the signal at the connector, with its ground via right beside it, and the signal passes the TVS pad before going on to the chip (a “Kelvin” connection). The series resistor, if any, goes after the TVS.
- Low-capacitance TVS arrays (under 1 pF) for fast data lines; larger ones for slow lines and power inputs.
- Keep the ESD path away from the circuit: the discharge current should flow from the connector through the TVS to chassis or ground and never across the logic.
- Add a clearance (a spark gap) or a chassis ground ring around connectors on enclosures.
Pre-compliance and fixes
- Design in the margin: do not wait for the test lab: layout rules, filters at connectors and slower edges cost cents; a respin costs weeks.
- Pre-compliance: a near-field probe set and a spectrum analyzer (or a cheap tracking tool) find the noisy parts early; compare against a known-good board.
- Quick fixes when a harmonic fails: a series resistor on the offending clock, a ferrite bead on the cable, a capacitor across the connector, a ground strap from the board to the chassis, and shielding cans.
- Documentation: the limits depend on the product and the market (FCC Part 15, CISPR 32/EN 55032, EN 61000-6-x): check which apply.
Troubleshooting
| Symptom | Likely cause | What to do |
|---|---|---|
| Overshoot and ringing on a clock | Unterminated transmission line | Add series termination at the driver; shorten the trace |
| Data errors that depend on a neighboring signal | Crosstalk | Increase spacing; add a plane; shorten the parallel run |
| Fails radiated emissions at a clock harmonic | Loop radiation or a cable carrying noise | Reduce loop area; filter the cable; slow the edge |
| Board resets when touched or when a cable is plugged in | ESD | TVS at the connector with a short ground path |
| USB device not recognized | Pair impedance, a stub, or the wrong termination | Check the 90 Ω pair, no stubs, 1.5 kΩ pull-up on D+ in the right place |
| Spikes at switch-on of a motor or relay | Inductive kick | Flyback diode or snubber at the load; keep the loop small |
Related
- PCB Design and Layout: the overview of this guide.
- Routing, Vias and Return Paths: return paths and vias.
- Power, Ground and Decoupling: decoupling and the hot loop.
- Electronics Fundamentals: the circuits themselves.
FAQ
When do I need to worry about signal integrity?
When the trace is longer than about one sixth of the length of the signal edge: roughly 28 mm for a 1 ns edge on FR-4. It is the edge speed, not the clock frequency, that counts.
What is the best termination?
Series termination at the driver for point-to-point CMOS (R = Z0 − R driver); parallel termination for buses and differential links.
Why does my board fail radiated emissions?
Usually a clock or switching harmonic radiating from a loop or from a cable that carries common-mode noise. Reduce the loop areas, slow the edges and filter the cables at the connector.
Where do I put an ESD diode?
Directly at the connector, between the connector pin and everything else, with a short, low-inductance connection to ground.
What is the 3W rule?
Space traces at least three trace widths center to center (two widths clear) to reduce crosstalk to about a tenth of what touching traces give; a closer ground plane is even better.
References
- Ott, H. W., Electromagnetic Compatibility Engineering, Wiley (loop and common-mode radiation).
- Johnson, H. and Graham, M., High-Speed Digital Design, Prentice Hall; Bogatin, E., Signal and Power Integrity: Simplified.
- IEC 61000-4-2 (ESD immunity); CISPR 32 / EN 55032; FCC 47 CFR Part 15 Subpart B.
Last reviewed: October 2026. The formulas are estimates for a single harmonic and simple geometries: real emissions must be measured against the limits that apply to your product.