Layer Stack-up and Impedance

Two, four and six layer boards, dielectrics, microstrip and stripline impedance, differential pairs and what to ask the fabricator.

On this page

Why the stack-up comes first
Two, four and six layers
FR-4 and the dielectric constants
Controlled impedance: microstrip
Stripline and differential pairs
How accurate is the impedance?
Loss and delay
What to ask the fabricator
Troubleshooting
FAQ

Why the stack-up comes first

The stack-up is the order and thickness of the copper and insulating layers. It decides the impedance of every trace, how close each signal is to its return plane, how well the board resists noise and how much it costs. It must be chosen before routing begins, because changing it moves every trace width.

Typical 2, 4 and 6 layer stack-ups, to a common scale.

Two, four and six layers

Layers	Typical use	Notes
2	Simple, slow, low-pin-count boards; power electronics with heavy copper	Pour ground on both sides; the return path is the pour and it is easy to break
4 (signal, ground, power, signal)	Microcontroller boards with USB, SPI at tens of MHz, mixed signals	A solid ground plane under the top signal layer solves most noise problems
6	Dense digital, DDR memory, fine-pitch BGAs, RF with shielding	Two extra routing layers sandwiched between planes (stripline)
8 and more	Servers, phones, high pin-count BGAs	HDI (micro vias) and controlled impedance throughout

Board	Relative cost (typical, prototype services)	Use
2-layer	1.0×	Simple, slow, low-density boards
4-layer	about 2 to 2.5×	Microcontrollers, USB, most mixed-signal boards
6-layer	about 3.5 to 4×	Dense digital, DDR, many BGAs
8-layer and more	about 6× and up	Servers, phones, HDI

Four-layer rule: L1 signal and parts, L2 solid ground, L3 power (split into areas), L4 signal. Keep the prepreg between L1 and L2 thin (0.1 to 0.2 mm) so that the signals are close to the ground plane.
Symmetry: make the stack-up symmetrical about its center (same copper weight and dielectric above and below) so that the board does not bow when it heats.
Never split the ground plane under fast signals (see Routing, Vias and Return Paths); put power on the plane next to ground, so that the pair forms a small capacitor that helps decoupling.
Use the fabricator’s stack-ups: they publish thicknesses that they stock (their “standard” 4-layer pressing).

Worked example: capacitance between planes

Two planes separated by a 0.21 mm prepreg of εr = 4.3 form a capacitor: C = ε₀ ε_r A ÷ d.
Per square centimeter: 8.854×10⁻¹² × 4.3 × 10⁻⁴ ÷ 0.21×10⁻³ = 18 pF per cm².
A 40 × 30 mm board has 12 cm² of overlapping plane, about 218 pF = 0.2 nF: useful above 100 MHz as a very low inductance capacitor, but no replacement for the 100 nF parts (see Power, Ground and Decoupling).

FR-4 and the dielectric constants

Material	εr (typical, 1 GHz)	Loss tangent	Use
FR-4 (standard)	4.2 to 4.6 (quoted 4.3 here)	0.02	Nearly everything below 1 GHz
High-Tg FR-4 (Tg 170 °C)	4.2 to 4.5	0.015 to 0.02	Lead-free assembly, heavy rework
Mid-loss and low-loss laminates (Isola, Megtron)	3.4 to 3.8	0.004 to 0.01	High-speed serial links over several GHz
PTFE (Rogers RO4350B, RO3003)	3.0 to 3.7	0.001 to 0.004	RF and microwave
Polyimide (flex)	3.2 to 3.5	0.002 to 0.02	Flexible boards
Aluminum core (MCPCB)	2.5 to 4 (dielectric)	—	LED lighting, power parts

The dielectric constant of FR-4 varies with frequency, resin content and glass weave. Ask for the figure your fabricator’s stack-up uses at the signal frequency.

Controlled impedance: microstrip

A trace over a plane is a transmission line with a characteristic impedance Z₀. When a signal’s edge is fast compared with the trace length (see Signal Integrity and EMC) the line should be matched to the driver and the receiver, which are usually designed for 50 Ω single-ended or 90 to 100 Ω differential. The IPC-2141 formula for a microstrip (trace on the outer layer over a plane) is:

Z₀ = 87 ÷ √(ε_r + 1.41) × ln[5.98 h ÷ (0.8 w + t)]

A 3 mm trace on 1.6 mm FR-4 has an impedance of about 50 Ω.

Worked example: 50 Ω on a two-layer and a four-layer board

Two-layer, h = 1.6 mm, εr = 4.3, t = 0.035 mm: solving gives w = 2.99 mm (check: Z = 50.0 Ω). That is a very wide trace, which is why impedance control on a two-layer board is rare.
Four-layer, h = 0.21 mm: w = 0.354 mm (about 14 mil), an easy width. The closer plane means narrower traces for the same impedance.
The ratio w ÷ h is about 1.87 in both cases: it depends only on the ratio, so halving the height halves the width.

Impedance against trace width for two dielectric heights.

Height h to the plane	Width for 50 Ω	w ÷ h
0.1 mm	0.146 mm	1.46
0.2 mm	0.335 mm	1.67
0.3 mm	0.524 mm	1.75
0.5 mm	0.903 mm	1.81
1.0 mm	1.849 mm	1.85
1.6 mm	2.985 mm	1.87

Stripline and differential pairs

A stripline runs on an inner layer between two planes. It is better shielded and radiates less than a microstrip, but is slower to route (vias) and its impedance depends on both distances.

Z₀ = 60 ÷ √ε_r × ln[4 b ÷ (0.67 π (0.8 w + t))]

Worked example: stripline and a USB pair

Stripline with planes 0.40 mm apart, εr = 4.3: for 50 Ω, w = 0.125 mm (check: Z = 50.0 Ω). A thin line like this suits fine-pitch BGAs.
A differential pair carries opposite signals on two coupled traces. USB, Ethernet and many serial links use 90 Ω (USB) or 100 Ω (Ethernet, LVDS) differential. With the approximation Z_diff ≈ 2 Z₀ (1 − 0.48 e^{−0.96 s/h}), a pair on the 0.21 mm prepreg with a spacing s = 0.15 mm needs w = 0.264 mm: Z₀ of each trace = 59.4 Ω, Z_diff = 90.0 Ω.
With a wider spacing s = 0.30 mm the traces couple less and need w = 0.340 mm: the pair is wider and takes more room. Fabricators’ field solvers give a more accurate answer, so send them the target and let them adjust the widths.

Keep the pair together, with constant spacing, equal length (within about 0.1 to 0.5 mm for USB 2.0 and 1 mm for most slow links) and no splits in the plane beneath.
Route differential pairs symmetrically through vias and connectors; add one ground via beside each signal via.
Do not use a stub or a sharp corner: use 45° or rounded bends (see Routing, Vias and Return Paths).

How accurate is the impedance?

Real impedance varies with the dielectric thickness (±10 %), the dielectric constant (±5 %) and the etched width (±0.025 mm). A fabricator typically offers ±10 % on controlled-impedance lines (±5 % at extra cost).

Worked example: tolerance of the 4-layer 50 Ω line

Nominal: w = 0.354 mm, h = 0.21 mm, Z = 50.0 Ω.
Prepreg 10 % thicker (h = 0.231 mm): Z = 53.5 Ω (+3.5 Ω); 10 % thinner: 46.2 Ω.
εr 5 % low (4.1): Z = 51.0 Ω; 5 % high (4.5): Z = 49.1 Ω.
Width 0.025 mm too wide: Z = 52.4 Ω; too narrow 47.8 Ω.
Combining the three at random (root-sum-square): about ± 4.2 Ω = ± 8.4 %: within the ±10 % that a fabricator quotes, though the worst case of all three together is larger.

Loss and delay

Signals travel more slowly on a board than in free space, by the factor 1 ÷ √ε_eff, and they lose energy to the dielectric and the copper. The dielectric loss in dB per unit length is α_d = 27.3 × f × √ε_eff × tan δ ÷ c.

Worked example: delay and loss on the four-layer line

ε_eff for w = 0.35 mm, h = 0.21 mm is 3.23, so the delay is 6.0 ps/mm (about 152 ps per inch). A stripline in the same material is slower: 6.9 ps/mm.
A 100 mm trace has a delay of 599 ps. A 1 ns edge reaches a transmission-line length of about 28 mm (one sixth of the edge length, see Signal Integrity and EMC).
Loss in standard FR-4 (tan δ = 0.02) and a low-loss laminate (0.004):

Frequency	FR-4 (tan δ 0.02)	Low-loss (tan δ 0.004, εr 3.6)
100 MHz	0.33 dB/m (0.01 dB/in)	0.06 dB/m (0.00 dB/in)
1 GHz	3.27 dB/m (0.08 dB/in)	0.60 dB/m (0.02 dB/in)
5 GHz	16.36 dB/m (0.42 dB/in)	3.02 dB/m (0.08 dB/in)

Dielectric loss alone is only part of the total; copper loss (skin effect and roughness) adds, and dominates in narrow traces below about 1 GHz. FR-4 is fine to a few hundred MHz, marginal at several GHz over long traces.

What to ask the fabricator

Their stack-up for the layer count and thickness, with the dielectric thicknesses and εr they use.
Controlled-impedance service: give them the target (50 Ω single, 90 Ω differential), the layers, and let them set the widths and spacings; ask for the test coupon and the report.
Copper weight on each layer (1 oz outer finishes at about 35 µm, inner 0.5 oz is standard).
Material: FR-4 Tg 135 or 170, or a low-loss laminate, and the surface finish (HASL, ENIG, OSP; see Manufacturing Rules, Files and Design Review).
Tolerances: total board thickness (±10 %), impedance (±10 %) and registration.

Troubleshooting

Symptom	Likely cause	What to do
Impedance far off target	Stack-up different from the one assumed	Use the fabricator’s stack-up and let them set widths
Board bows after reflow	Unbalanced copper or stack-up	Make the stack-up symmetrical; balance copper
Eye diagram closed on a long trace	Loss and reflections	Shorten; lower loss laminate; fix termination
Fast signals noisy on a 2-layer board	No continuous return plane	Add a ground pour and stitching vias or go to 4 layers
Differential pair mismatch	Different lengths or coupling	Match lengths; keep spacing constant
Trace width limit reached	Required width too narrow for the process	Use a thicker dielectric or relax the target

PCB Design and Layout: the overview of this guide.
Design Workflow: Schematic to Board: choosing the layer count early.
Signal Integrity and EMC: why impedance matters.
Manufacturing Rules, Files and Design Review: the fabricator’s limits.

FAQ

How many layers should my PCB have?

Two for simple slow circuits, four for microcontroller and USB boards, six or more for dense digital and DDR. The cost of four layers is about twice that of two.

What trace width gives 50 Ω?

It depends on the distance to the plane: about 3 mm on a 1.6 mm two-layer board and about 0.35 mm over a 0.21 mm prepreg on a four-layer board. Ask the fabricator for their stack-up.

Do I need controlled impedance?

Only when the traces are electrically long compared with the edge (USB, Ethernet, DDR, RF, fast clocks). Slow signals do not need it.

Is FR-4 good enough?

Yes for nearly everything up to a few hundred MHz and for USB 2.0. For multi-gigabit links over long traces use a low-loss laminate.

What is a prepreg?

A glass cloth soaked in partly cured resin that is pressed between copper layers to bond a multilayer board; it sets the distance between layers.

References

IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards; IPC-4101 (laminate specifications).
Bogatin, E., Signal and Power Integrity: Simplified, Prentice Hall.
Johnson, H. and Graham, M., High-Speed Digital Design, Prentice Hall (transmission lines).
Fabricators’ published stack-ups and impedance calculators (JLCPCB, PCBWay, OSH Park).

Last reviewed: October 2026. The formulas are approximations (a few percent for the microstrip, more for differential pairs): fabricators use field solvers.