Routing, Vias and Return Paths
Routing order, vias and their inductance, return current, split planes, stubs and corners.
Routing order and strategy
Route in order of importance, not in order of convenience. The autorouter is a tool for the easy 80 %, not a substitute for thinking about the hard 20 %.
- 1. Power and ground: planes and wide traces first (see Power, Ground and Decoupling).
- 2. Critical signals: clocks, differential pairs, analog inputs and anything with an impedance or length rule, routed by hand on the layer next to a ground plane.
- 3. The rest: buses and control lines; let the router do them, then tidy.
- 4. Fix up: cleanups, stitching vias, teardrops, silkscreen and checks.
- Two-layer boards: run most traces horizontally on one side and vertically on the other, so that they cross at right angles (a small coupling) and keep the layer you do not route as a ground pour.
- Four-layer boards: route on L1 and L4, with L2 (ground) as the reference for both; use L3 only for power and a few signals.
- Keep traces short and direct, avoid loops and branches, and do not run in parallel for long over the same distance.
- Leave space: do not use the minimum rules everywhere; a route at 0.25 mm trace and space is more robust than the 0.127 mm minimum.
Return paths: the idea that explains most noise
Current always flows in a loop: out along the trace and back along the nearest path it can find. At low frequency the return current spreads out over the lowest resistance route. At high frequency (above a MHz or so) it follows the path of lowest inductance, which is directly under the trace on the adjacent plane. The smaller the loop between a signal and its return, the less the signal radiates and the less noise it picks up.
Worked example: what a slot costs
- A 50 mm trace runs 0.2 mm above its plane (a four-layer board). The loop area with a direct return is about 50 × 0.2 = 10 mm².
- Now cut a slot across the plane so that the return current detours 30 mm: the loop area becomes 50 × 30 = 1 500 mm², 150 times larger.
- Radiated field is proportional to the loop area. For a 100 MHz harmonic carrying 5 mA at 3 m: with the direct return E = 12.8 dBµV/m; with the detour 56.4 dBµV/m (43.5 dB more). The FCC Class B limit at 3 m in that band is 43.5 dBµV/m: the slotted board would fail by 12.9 dB (estimate for one harmonic).
- The same loop picks up noise from outside by the same factor: a large loop is a better antenna in both directions.
- Never route a fast signal over a slot, a split in the plane or the edge of a pour: give it an unbroken ground plane beneath.
- When a signal changes layers, put a ground via within 1 to 2 mm of its signal via, so that the return can change planes with it. If the two reference planes are at different voltages (ground and power), add a decoupling capacitor next to the via.
- Do not split the ground plane for “analog” and “digital”: use placement and one plane (the return current stays under its trace anyway).
- Keep the plane continuous under connectors and across the board, and avoid rows of vias that perforate it like a postage stamp: leave copper between the anti-pads.
Vias: size, inductance and layer changes
A via adds inductance, capacitance and resistance to the path. For signals the main effects are the inductance and the stub; for power the resistance and inductance; and for heat the thermal resistance (see Thermal Design on the Board).
L ≈ 5.08 h [ln(4h ÷ d) + 1] nH, C ≈ 1.41 εr T D1 ÷ (D2 − D1) pF
Worked example: a standard through via
- Via 0.3 mm in a 1.6 mm board: L = 5.08 × 0.063 × [ln(4 × 0.063 ÷ 0.0118) + 1] = 1.30 nH.
- With a pad of 0.6 mm and an anti-pad of 1.0 mm in the planes it has a capacitance of 0.57 pF, so its own impedance is √(L ÷ C) = 48 Ω.
- Reactance: 0.08 Ω at 10 MHz, 0.82 Ω at 100 MHz and 8.2 Ω at 1 GHz. A via in the path of a 100 nF capacitor therefore matters above 10 MHz: use two vias per pad for decoupling capacitors and put them right at the pad.
- DC resistance (25 µm plating): 1.08 mΩ per via.
| Via length | Drill | Inductance | DC resistance |
|---|---|---|---|
| 1.60 mm | 0.3 mm | 1.30 nH | 1.1 mΩ |
| 1.60 mm | 0.2 mm | 1.43 nH | 1.6 mΩ |
| 1.00 mm | 0.3 mm | 0.72 nH | 0.7 mΩ |
| 0.80 mm | 0.2 mm | 0.60 nH | 0.8 mΩ |
| 0.21 mm | 0.1 mm | 0.13 nH | 0.4 mΩ |
- Use through vias (0.3 mm drill, 0.6 mm pad) unless you need the density of blind, buried or micro vias; they cost more.
- Minimize the number of vias on a signal: each is an impedance discontinuity.
- Via-in-pad (under a BGA or QFN pad) must be filled and capped, or the solder runs down the barrel.
- Tent or plug vias that are not meant for probing, so that solder does not run through them.
- Keep vias out of the pads of small SMD parts, and out of the path of a high-current trace unless there are enough of them.
Worked example: the stub of a through via
- A signal that enters a via at the top and leaves at an inner layer leaves a stub of unused barrel below it. The stub is a quarter-wave resonator at f = c ÷ (4 L √εr).
| Stub | Length | Resonance |
|---|---|---|
| Full 1.6 mm through via, signal on top | 1.5 mm | 24 GHz |
| Signal changes top to inner layer 3 | 1.2 mm | 30 GHz |
| Back-drilled to 0.3 mm | 0.3 mm | 120 GHz |
Resonances above several GHz do not matter for USB 2.0 or I2C, but matter for 10 Gb/s links, where designers use blind vias, thinner boards or back-drilling.
Planes, pours and stitching vias
A copper pour (a filled polygon) connected to ground on the outer layers gives a return path, shields, spreads heat and balances the copper. Connect pours to the ground plane with stitching vias, spaced at no more than λ/20 of the highest frequency of concern, so that isolated copper does not resonate.
| Frequency | Wavelength in the board (εeff 3.1) | Stitching spacing (λ ÷ 20) |
|---|---|---|
| 100 MHz | 1 703 mm | 85.1 mm |
| 500 MHz | 341 mm | 17.0 mm |
| 1 000 MHz | 170 mm | 8.5 mm |
| 3 000 MHz | 57 mm | 2.8 mm |
- No islands: remove unconnected copper: it acts as an antenna and it can break away.
- Ground the edge: a row of vias around the edge of a ground pour (a “fence”) reduces edge radiation on fast boards.
- Thermal relief: small pads in a pour are connected with spokes so that they can be soldered (see Through-Hole Soldering), but use direct connections for high-current and RF grounds.
- Avoid thin necks and long dead-ends in pours.
Corners, stubs and branches
- Use 45° bends or arcs, not 90°. A square corner has extra capacitance and, at manufacture, acid can be trapped; the effect on signals is small below 1 GHz but 45° looks better and routes shorter.
- Avoid stubs and T-branches on fast nets: a clock to several loads should run as a daisy chain or a star with equal legs, with the termination at the end.
- Teardrops at pad-to-trace joins strengthen the connection against drill breakout and thermal stress.
- Do not run traces under crystals, inductors or switching nodes.
Worked example: a 90° corner against two 45° corners
- A 0.25 mm trace with a 90° turn between two 5 mm legs has a path of 10 mm. With two 45° bends (chamfer of 2 mm on each side) the path is 8.83 mm: 1.17 mm shorter.
- The corner’s extra capacitance is a fraction of a picofarad on a 0.25 mm trace: negligible. Rounded corners matter for appearance and etching, not for impedance, until the multi-gigabit range.
Length matching and groups
Signals that must arrive together (a parallel bus, a differential pair, DDR data bytes) are routed to equal lengths. The allowed skew comes from the timing budget; the length difference is skew ÷ delay per mm. Delay on the 0.2 mm microstrip of the four-layer board is about 6.0 ps/mm.
| Allowed skew | Length mismatch |
|---|---|
| 200 ps | 33.38 mm |
| 50 ps | 8.34 mm |
| 10 ps | 1.67 mm |
- Differential pairs: match the two lengths to better than the signal’s rise time ÷ 10 (about 0.1 to 0.5 mm for USB 2.0) and match at the point where they differ (add the serpentine near the mismatch).
- Parallel buses (SPI, parallel LCD): need matching only above about 50 MHz.
- Meanders: use gentle serpentines with spacing of at least 3 trace widths between legs, so that they do not couple to themselves.
Escaping from fine-pitch parts
The number of traces that can pass between pads limits how a dense part is routed. With 0.15 mm trace and 0.15 mm space (a 0.3 mm pitch):
| Pad pitch | Traces between pads |
|---|---|
| 2.54 mm header (pad 1.7 mm) | 2 traces |
| 1.27 mm SOIC (pad 0.6 mm) | 1 trace |
| 0.65 mm TSSOP (pad 0.4 mm) | 0 (none: fan out with vias) |
| 0.5 mm QFP (pad 0.3 mm) | 0 (none: fan out with vias) |
- Fan out with a via next to each pin on dense parts, then route on another layer (“dog-bone” fan-out).
- Neck down traces to a narrow width only where they pass between pads.
- BGAs: a 1.0 mm pitch needs a via in the gap between pads; a 0.8 mm pitch needs 0.2 mm vias and fine design rules; below that use via-in-pad.
Before you call it done
- Design-rule check clean, with the fabricator’s rules loaded.
- Ground plane unbroken under every fast signal; no signal crosses a slot.
- Stitching vias and the fence in place; no copper islands.
- Decoupling capacitors connected with short, wide traces and vias.
- Differential pairs matched and constant in spacing.
- Silkscreen legible and clear of pads; reference marks match the assembly drawing.
- 3D view: parts, connectors and holes fit the case.
Troubleshooting
| Symptom | Likely cause | What to do |
|---|---|---|
| Clock radiates, fails EMC test | Return path broken or large loop | Route the clock over solid ground; shorten it; add series resistor |
| Ground bounce on the analog input | Return currents crossing the analog area | Re-place noisy parts; keep returns separate by placement |
| Signal ringing | Long unterminated trace, stub or via | Shorten; series termination; remove the stub |
| Via opens or cracks in service | Too small, thermal stress | Larger drill; more vias; thicker plating |
| Solder wicks through a via-in-pad | Via not filled | Specify filled and capped vias, or move the via off the pad |
| Board will not route | Poor placement or too few layers | Re-place; add a layer (see Layer Stack-up and Impedance) |
Related
- PCB Design and Layout: the overview of this guide.
- Component Placement and Floorplanning: place first, then route.
- Power, Ground and Decoupling: power and decoupling.
- Signal Integrity and EMC: termination and crosstalk.
FAQ
What is a return path?
The route the current takes back to its source. At high frequency it runs directly under the signal trace on the nearest plane; the smaller the loop, the quieter the board.
Can I route over a split in the ground plane?
Not with a fast signal: the return current must detour round the split, making a big loop. Keep the plane unbroken, or add a stitching capacitor where a signal must cross.
How much inductance does a via have?
About 1 to 1.5 nH for a standard 0.3 mm via in a 1.6 mm board, which is 0.8 Ω at 100 MHz.
Are 90 degree corners bad?
Not electrically below about 1 GHz, but 45° bends or arcs are neater, shorter and manufacture better.
How far apart should stitching vias be?
Less than one twentieth of a wavelength at the highest frequency of concern: about 8 mm at 1 GHz on FR-4.
References
- Johnson, H. and Graham, M., High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall (via models).
- Ott, H. W., Electromagnetic Compatibility Engineering, Wiley (return currents, radiation from loops).
- Bogatin, E., Signal and Power Integrity: Simplified, Prentice Hall; IPC-2221B and IPC-2141A.
Last reviewed: October 2026. The via and radiation formulas are estimates, and the field strengths are for one harmonic of a simple loop; real emissions need measurement.