Manufacturing Rules, Files and Design Review
Fabricator limits, annular rings, mask dams, panels, output files, testing and a design-review checklist.
Fabricator capabilities and your rules
Every fabricator publishes what it can make. Their standard process is cheap and reliable; the advanced one (finer lines, smaller holes) costs more and has lower yield. Design to the standard process unless you must not. The values below are typical for low-cost prototype services (see PCB Prototyping); load your fabricator’s own rules into the design-rule check.
| Item | Standard process (typical) | Advanced (typical) |
|---|---|---|
| Trace / space | 0.127 / 0.127 mm (5 / 5 mil); design for 0.15 or more | 0.09 / 0.09 mm (3.5 mil) or less |
| Drill (finished) diameter | 0.3 mm minimum | 0.2 mm (0.15 mm laser) |
| Annular ring | 0.13 mm minimum (0.15 to 0.2 mm design) | 0.075 to 0.1 mm |
| Board thickness | 0.8, 1.0, 1.2, 1.6 (standard), 2.0 mm | 0.4 to 3.2 mm |
| Outer copper | 1 oz (35 µm), 2 oz option | 3 oz and more (heavy copper) |
| Solder-mask dam | 0.1 mm (green) to 0.15 mm (other colors) | 0.075 mm |
| Silkscreen | 1.0 mm text height, 0.15 mm line | 0.8 mm and 0.1 mm |
| Copper to board edge | 0.3 mm (0.5 mm preferred) | 0.2 mm |
| Smallest slot | 0.8 mm (router limit) | 0.5 mm |
| Hole to hole | 0.5 mm edge to edge | 0.25 mm |
| Registration (layer to layer) | ±0.075 to 0.1 mm | ±0.05 mm |
Holes, annular rings and aspect ratio
The annular ring is the copper left around a drilled hole. The drill can land a little off (registration), so the pad must be large enough that the hole never breaks out of it. A plated hole also needs the pad to survive soldering and rework.
Pad diameter = hole + 2 × (minimum ring + registration)
| Hole | Finished drill | Minimum pad (calculated) | Recommended pad (hole + 0.6 mm) |
|---|---|---|---|
| Signal via | 0.30 mm | 0.71 mm | 0.90 mm |
| Small via | 0.20 mm | 0.61 mm | 0.80 mm |
| Header pin 1.0 mm | 1.00 mm | 1.41 mm | 1.60 mm |
| Header hole for 0.64 mm square pin | 1.10 mm | 1.51 mm | 1.70 mm |
| Mounting hole M3 (plated) | 3.20 mm | 3.61 mm | 3.80 mm |
Fabricators drill a hole 0.1 mm larger than the finished size to allow for the plating: specify the finished hole size (the size after plating) on your drill file and in your drawing, unless the fabricator says otherwise.
Worked example: via size and aspect ratio
- The aspect ratio is board thickness ÷ drill diameter; plating becomes hard above about 8 to 10. For a 1.6 mm board:
| Drill | Aspect ratio | Status |
|---|---|---|
| 0.30 mm | 5.3 : 1 | standard |
| 0.20 mm | 8.0 : 1 | standard |
| 0.15 mm | 10.7 : 1 | too high: thinner board or blind via |
- A 0.3 mm via with a 0.6 mm pad has a ring of 0.15 mm: just above the 0.13 mm minimum, so a standard design uses 0.3 / 0.6 mm and a conservative one 0.3 / 0.7 mm.
- A 0.2 mm drill in 1.6 mm FR-4 is 8:1: possible, but costs more at some services. On a 0.8 mm board it is 4:1 (easy).
- Plated slots and holes of non-round shape go in the same file but check the fabricator’s limits.
Solder mask, silkscreen and finish
The solder mask (the green or other colored lacquer) covers the copper except where openings expose pads. The opening is made slightly larger than the pad (the mask expansion, typically 0.05 mm) to allow for registration. The strip of mask left between two pads is the mask dam; it stops the solder from bridging, but needs a minimum width.
Worked example: do the pads keep a mask dam?
- Dam = pad gap − 2 × mask expansion = (pitch − pad width) − 2 × 0.05 mm. With a minimum dam of 0.10 mm:
| Part | Pad gap | Mask dam | Result |
|---|---|---|---|
| SOIC 1.27 mm | 0.67 mm | 0.57 mm | dam possible |
| TSSOP 0.65 mm | 0.25 mm | 0.15 mm | dam possible |
| QFP 0.5 mm | 0.20 mm | 0.10 mm | dam possible |
| QFP 0.4 mm | 0.18 mm | 0.08 mm | no dam: open the mask as a group |
| BGA 0.8 mm (pad 0.4) | 0.40 mm | 0.30 mm | dam possible |
Where the dam cannot be made, the fabricator opens the mask in one long slot along the pads; the solder bridges are then prevented by flux and process (see Surface-Mount Soldering). A 0.4 mm pitch QFP is usually done this way.
| Surface finish | Flatness | Shelf life | Notes |
|---|---|---|---|
| HASL (lead-free) | Poor: domed pads | 12 months | Cheapest; not for pitch under 0.65 mm or BGAs |
| ENIG (gold over nickel) | Excellent | 12 months | Fine pitch, BGAs, wire bonding; costs more; “black pad” risk, so use a good fabricator |
| OSP (organic coating) | Excellent | 3 to 6 months | Cheap, lead-free; limited reflow cycles; no re-work after storage |
| Immersion silver / tin | Excellent | 6 to 12 months | Fine pitch; tarnish and whisker concerns; keep sealed |
| Hard gold | Excellent | Long | Edge connectors and switches; costly |
- Silkscreen: text of at least 1 mm, line 0.15 mm; reference designators for each part, polarity marks, pin 1 and the board revision; keep it off pads (the fabricator clips it).
- Solder mask color: green is the most tested and the cheapest; black and white look good but have wider dams and reduce contrast for inspection.
- Fiducials and tooling holes: bare copper, no mask, 1 mm with a 2 mm clear mask opening.
Panels, tabs and fiducials
Small boards are made and assembled in panels that hold several copies in a frame, so that machines can handle them. The boards are separated by V-scoring (a V-groove from both sides; boards touch, straight cuts only) or tab routing (boards separated by a gap with a few narrow tabs, with perforated “mouse bites”). A prototype service will panelize for you, usually at no cost.
Worked example: a panel of the sensor board
- Board 45 × 30 mm in a 4 × 3 array with 2.0 mm gaps (tab-routed) and 5 mm rails: panel = 196 × 104 mm for 12 boards.
- Utilization = 12 × 45 × 30 ÷ (196 × 104) = 79 %; the rest is rails and gaps.
- Fabricators’ work panels are about 18 × 24 inch (457 × 610 mm): about 10 of these customer panels fit (with 80 % usable area), which is why the price per board falls with quantity.
- The cost of a prototype run is largely set-up plus area (illustrative values: $30 plus $0.05 per cm² for a two-layer board with a factor of 1.6 for the real process): 5 boards at $7.08 each; 10 boards at $4.08 each; 50 boards at $1.68 each; 100 boards at $1.38 each. Order more than you need: the first boards pay for the set-up.
- Keep parts and traces 3 mm from V-score lines and 1 mm from tab routing edges, and keep tabs clear of copper.
- Put three fiducials on the panel rails, and local ones on the board for fine-pitch parts.
- Leave a 5 mm rail on the long edges for the assembly line to hold the panel.
Output files
The fabricator makes the board from Gerber files (one per layer, RS-274X format) and an Excellon drill file. Every layout program can export them; most fabricators accept a single zip of all files.
| Layer | KiCad name | Older extension | What it is |
|---|---|---|---|
| Top copper | F_Cu.gbr | GTL | Copper pattern, top |
| Bottom copper | B_Cu.gbr | GBL | Copper pattern, bottom |
| Inner layers | In1_Cu.gbr, In2_Cu.gbr | G2, G3 | Four-layer boards |
| Solder mask top and bottom | F_Mask.gbr, B_Mask.gbr | GTS, GBS | Openings in the mask |
| Silkscreen | F_Silkscreen.gbr, B_Silkscreen.gbr | GTO, GBO | Text and outlines |
| Paste (stencil) | F_Paste.gbr, B_Paste.gbr | GTP, GBP | Only if you order a stencil |
| Board outline | Edge_Cuts.gbr | GKO / GML | Shape and cut-outs |
| Drill file | PTH.drl, NPTH.drl | TXT / DRL | Plated and non-plated holes (Excellon) |
| Netlist (optional) | IPC-D-356 | IPC | Lets the fabricator check shorts and opens |
- Check the files before you send them: open the Gerbers in a viewer (the fabricator’s online viewer or a free viewer such as gerbv or KiCad’s Gerber viewer), look at each layer, check the outline and the holes, and compare to the design.
- Name the files and the zip with the board name and revision.
- Write the fabrication notes (a readme): layers, thickness, copper weight, finish, mask color, impedance requirements and tolerances.
- Use the same units and origin for all files; export the drill file with the same origin as the Gerbers.
Files for assembly
- Bill of materials (BOM): one line per unique part: reference designators, quantity, value, footprint, manufacturer, manufacturer part number and supplier number. A BOM that lists exact manufacturer part numbers avoids substitutions.
- Pick-and-place (component placement) file: reference, X, Y, rotation and side for every part. Rotation conventions differ between programs: check the assembler’s preview.
- Assembly drawing: a PDF with the outline, parts, polarity and notes (for hand assembly and inspection).
- Stencil file: the paste layers, and the stencil thickness (usually 0.12 mm; 0.1 mm for fine pitch; see Solder Alloys, Flux and Paste).
- Special instructions: parts not to place, parts to hand-solder, glue, conformal coating and test.
Design for test
Worked example: test pads for the sensor board
- The board has about 57 nets. A reasonable test strategy gives a pad to about 40 % of them (the rest are tested through other nets): 23 pads of 1.0 mm. They need 18 mm² of board.
- Place the pads on the same side, on a 1.27 or 2.54 mm grid where possible, at least 1 mm from other parts, and do not cover them with mask or silkscreen. A flying-probe tester needs no fixture; a bed-of-nails fixture needs 1 mm pads at 2.54 mm centers.
- Also add a header for programming, test points on every power rail and a ground near each, and LEDs for the main states.
Design review checklist
Review the board with a fresh mind or a second person, using a written list. This list covers the main points; add to it every time a fault is found.
| Area | Check |
|---|---|
| Schematic | ERC clean; every net named; every pin used or marked unused; power pins connected; pull-ups and strap pins set; part values and ratings checked (voltage, power, tolerance) |
| Footprints | Every footprint checked against the data sheet; pin 1 and pin numbering; pad size; printed 1:1 and tried with the real part |
| Placement | Connectors and holes match the case; decoupling at the pins; crystal near the chip; heat and sensitive parts apart; test points |
| Routing | DRC clean with fabricator rules; widths for current; spacing for voltage; no slot under a fast signal; stitching vias; pair lengths |
| Power | Decoupling per pin; input protection; bulk capacitors; regulator layout from the data sheet; power-on sequencing |
| Thermal | Copper and vias for each warm part; the temperature at the maximum ambient |
| Mechanical | Board outline; hole sizes and positions; keep-outs; 3D fit in the enclosure; connector orientation |
| Silkscreen | Reference marks readable; polarity; revision and name; not on pads |
| Files | Gerbers and drill viewed; BOM complete with part numbers; pick-and-place orientation; fabrication notes |
| Test | Test points, programming header and bring-up plan (see Design, Testing and Troubleshooting) |
Troubleshooting
| Symptom | Likely cause | What to do |
|---|---|---|
| Fabricator reports a DFM issue | A rule below their capability | Relax the rule or pay for the advanced process; resubmit |
| Hole breaks out of the pad | Annular ring too small | Larger pad, 0.15 mm ring or more |
| Solder bridges on fine pitch | No mask dam | Check the dam; use a thinner stencil; better flux |
| Boards arrive with the wrong size holes | Plated and finished sizes confused | State finished hole size; check the drill file units |
| Parts rotated wrong in assembly | Pick-and-place rotation convention | Check the assembler’s preview; add a rotation column |
| Pads look different from the drawing | Mask expansion, finish thickness | Check the Gerbers in a viewer; ask the fabricator |
| Board is bowed after assembly | Unbalanced copper, thin board | Balance the copper; thicker board; panel support |
Related
- PCB Design and Layout: the overview of this guide.
- Worked Layouts: a complete worked design.
- PCB Prototyping: ordering, cost and lead time.
- Soldering: assembly.
FAQ
What files do I send to a PCB fabricator?
Gerber (RS-274X) files for each copper, mask, silkscreen and outline layer, and an Excellon drill file, usually in one zip. Add a netlist and fabrication notes if you can.
What is a good minimum trace width and spacing?
Design for 0.15 mm (6 mil) or more for the standard process, even though 0.127 mm (5 mil) is the minimum; wider is cheaper and more reliable.
What annular ring do I need?
At least 0.13 mm for the standard process; 0.15 to 0.2 mm in the design, which gives pads of about hole + 0.4 to 0.6 mm.
What is a panel?
A frame that holds several copies of a board so that machines can fabricate and assemble them, with tabs or V-score lines to break them apart.
Which surface finish should I use?
Lead-free HASL for cheap boards with larger parts, ENIG for fine pitch and BGAs, OSP for low cost and flat pads with a short shelf life.
References
- IPC-2221B (design); IPC-6012 (rigid boards: qualification and performance); IPC-A-600 (acceptability of printed boards); IPC-2581 and ODB++ (data exchange).
- Ucamco, The Gerber Layer Format Specification (ucamco.com).
- Fabricators’ published capabilities (JLCPCB, PCBWay, OSH Park, Eurocircuits) and DFM guidelines.
Last reviewed: October 2026. Capabilities and prices change: use your fabricator’s current published figures.