Worked Layouts
Three layouts worked through with numbers: a two-layer sensor board, a buck converter and a four-layer USB board.
Layout A: a two-layer USB sensor board
The board from earlier pages: a USB-C powered 3.3 V microcontroller board with an I2C sensor, two LEDs, a button and two headers, 36 parts and 137 pins on 45 × 30 mm (see Design Workflow: Schematic to Board and Component Placement and Floorplanning). A two-layer stack-up (1.6 mm, top signal and bottom ground pour) is enough: the pin density is 10 per cm² and the fastest signals are USB full speed and I2C.
Worked example: the numbers behind layout A
- Power: the 3.3 V rail supplies about 150 mA. The IPC-2221 width for 150 mA at +10 °C is only 0.02 mm, so a 0.3 mm minimum is used for 3V3 (300 µm, 12 mil) and 0.5 mm for VBUS from the connector (USB allows 0.5 A: 0.12 mm).
- Regulator: the LDO drops 5.0 − 3.3 = 1.7 V at 150 mA: 0.26 W. On a SOT-223 with a 6 cm² pour (62 K/W) the rise is 16 K (see Thermal Design on the Board): fine, so a linear regulator is the simple choice.
- LEDs: 5 mA from 3.3 V with a 2.0 V forward drop: R = (3.3 − 2.0) ÷ 0.005 = 260 Ω (use 270 Ω).
- I2C: 4.7 kΩ pull-ups with 50 pF of bus capacitance give a rise time of 0.8473 × R × C = 199 ns, within the 300 ns limit of 400 kHz fast mode.
- Crystal: a 12 pF crystal with 3 pF stray capacitance needs 2 × (12 − 3) = 18 pF load capacitors (see Component Placement and Floorplanning), 5 mm from the chip.
- Decoupling: 6 ceramic capacitors of 100 nF (one per supply pin and the analog and sensor supply), each within 3 mm of its pin with a via to the ground pour beside it, a 10 µF at the regulator output and at VBUS (see Power, Ground and Decoupling).
- USB full speed: D+ and D− run 35 mm: delay 197 ps against an edge of 4 ns, whose critical length is 118 mm, so the pair is electrically short; route them together, equal in length, with the TVS at the connector (see Signal Integrity and EMC).
- Ground: a pour on the bottom layer with a pour on the top, joined by stitching vias every 8 to 10 mm, and no slots in the pour under the USB pair.
| Item | Choice | Why |
|---|---|---|
| Stack-up | 2 layers, 1.6 mm, 1 oz | Low pin density; slow signals |
| Rules | 0.2 / 0.2 mm trace and space; via 0.3 / 0.6 mm; 0.3 mm to the edge | Standard process, good yield |
| Net classes | Signal 0.2 mm; 3V3 0.3 mm; VBUS 0.5 mm | Current and drop |
| Finish | HASL or ENIG | TQFP at 0.8 mm pitch is fine with HASL |
| Assembly | By hand: pads 0.5 to 1 mm longer | See Soldering |
Layout B: a 12 V to 5 V, 2 A buck converter
A synchronous buck converter module on two layers: 12 V input, 5 V at 2 A, switching at 500 kHz. The converter IC is a 3 × 3 mm QFN with a thermal pad; it needs an inductor and ceramic capacitors. The layout is what makes or breaks it.
Worked example: the numbers behind layout B
- Duty cycle: D = Vout ÷ Vin = 5 ÷ 12 = 0.42.
- Inductor: for a ripple current of 30 % of the load (0.60 A) L = Vout (1 − D) ÷ (f ΔI) = 5 × 0.58 ÷ (500 kHz × 0.60 A) = 9.7 µH: use 10 µH (ripple 0.58 A, peak 2.29 A: choose a saturation current of 3 A or more).
- Output capacitor: 22 µF ceramic: ΔV = ΔI ÷ (8 f C) = 0.58 ÷ (8 × 500 kHz × 22 µF) = 6.6 mV.
- Input capacitor: its ripple current is Iout √(D (1 − D)) = 2 × 0.49 = 0.99 A RMS: a ceramic of 10 µF, 25 V is far enough (note the DC-bias derating at 12 V).
- Efficiency and heat: at 92 % the loss is 10.00 × (1 ÷ 0.92 − 1) = 0.87 W; if the IC accounts for 60 % (0.52 W) and has θJA = 40 K/W with nine thermal vias and a pour, it runs 21 K above ambient (see Thermal Design on the Board).
- Traces: input current averages 0.91 A (0.26 mm for +10 °C); the switch-node and output carry 2 A (0.78 mm): use 1.5 mm or a pour for both, short and wide.
- The hot loop: the switch turns off 2 A in 5 ns (0.4 A/ns, a knee of 70 MHz). With the 100 nF and 10 µF capacitors 2 mm from the pins (about 2 nH, a loop of 12 mm²) the spike is 0.80 V; with the capacitor 10 mm away (10 nH) it is 4.0 V (see Power, Ground and Decoupling).
- Order of placement: the converter IC; the input capacitors on the VIN and PGND pins; the inductor on SW; the output capacitors; the feedback divider away from the inductor and SW.
- Copper: a solid ground pour on the bottom layer under the converter, connected by vias at the PGND pads; the SW node as a small, short pour that is not larger than it needs to be.
- Feedback trace: from the output capacitor’s terminal, away from SW and the inductor, to the divider, on the quiet side.
- Follow the data sheet layout: copy its placement and adjust for your footprint sizes.
Layout C: a four-layer board with a USB 2.0 high-speed pair
A USB-C device board with a high-speed (480 Mbit/s) interface needs controlled impedance: 90 Ω differential. A four-layer stack-up with the ground plane directly under the top layer makes this easy and gives a quiet return path.
Worked example: the numbers behind layout C
- Stack-up: 1.6 mm, L1 signal, L2 ground (0.21 mm prepreg below L1), L3 power, L4 signal. The ground plane next to the top layer is the reference for the USB pair.
- Pair geometry: for Zdiff = 90 Ω on h = 0.21 mm with a spacing of 0.15 mm: w = 0.264 mm (Z0 of each trace 59.4 Ω, Zdiff 90.0 Ω; see Layer Stack-up and Impedance). Ask the fabricator to confirm with their stack-up.
- Length and skew: 40 mm of pair has a delay of 237 ps (5.9 ps/mm). A skew budget of about 25 ps allows 4.2 mm of mismatch; design for 0.5 mm (3 ps) for margin (see Routing, Vias and Return Paths).
- ESD: an 8 kV contact discharge (60 A peak, ~0.8 ns rise, see Signal Integrity and EMC) through 2 nH of trace gives 150 V on top of the 24 V clamp: place the low-capacitance TVS array right at the connector pins with a ground via beside it.
- Plane capacitance: L1 to L2 over the 45 × 30 mm board: C = ε0 εr A ÷ d = 245 pF, a small help for high-frequency decoupling.
- Cost: a four-layer board costs about 2.2 times the two-layer price of the same size at a prototype service (illustrative): worth it for USB high speed, a dense MCU or low-noise analog.
- Layer assignment: L1 signals and parts, L2 solid ground, L3 3.3 V and 5 V areas, L4 slow signals and a ground pour.
- USB pair routing: straight from the connector, 90 Ω, with stitching vias where it changes layer (avoid layer changes), no stubs and a clean ground plane beneath; the TVS before the common-mode choke, if used.
- Power: split the L3 power layer into areas, with decoupling between them; stitch the L2 plane with ground vias around the board’s edge.
- Shield: connect the connector shield to the chassis ground with a short path.
What the three have in common
| Aspect | A: sensor board | B: buck converter | C: USB high-speed |
|---|---|---|---|
| Layers | 2 | 2 (4 for noise-critical) | 4 |
| What decides the layout | Floorplan and decoupling | Hot loop and thermal pad | Pair impedance and return path |
| Key number | LDO rise 16 K | Spike 0.80 V vs 4.0 V | w = 0.264 mm for 90 Ω |
| Biggest risk | Wrong footprint | Large loop and heat | Broken plane under the pair |
| Review focus | Footprints, pin 1, decoupling | Copy the data-sheet layout | Stack-up confirmed with the fabricator |
Lessons, in the order to apply them
- Write the requirements, then check every footprint.
- Choose the stack-up before the first trace and let the fabricator confirm it.
- Place with intent: floorplan, connectors, then decoupling and crystals beside the pins.
- Route power and critical signals by hand, over unbroken planes.
- Size traces for current and drop, space for voltage, and set the rules before routing.
- Give heat a path: copper, vias and distance.
- Review with a list, view the Gerbers, order, and keep the design files and notes for the next revision.
Troubleshooting
| Symptom | Likely cause | What to do |
|---|---|---|
| First board does not power up | Short on a rail, reversed part, missing solder | Check resistance across each rail with the power off; inspect (see Soldering) |
| Converter noisy or hot | Hot loop too large; thermal pad not soldered | Move the input capacitor to the pins; reflow the pad; add vias |
| USB device not recognized | Wrong pair impedance, D+ and D− swapped, no pull-up | Check the pair, the schematic, the 5.1 kΩ CC resistors for USB-C |
| Microcontroller will not start | Crystal load capacitors, missing decoupling | Check the crystal and capacitors against the data sheet |
| Board works on the bench, fails in the case | Heat, or ESD and noise from cables | Test at the maximum ambient and with an ESD gun; add protection |
Related
- PCB Design and Layout: the overview of this guide.
- Manufacturing Rules, Files and Design Review: files and review before ordering.
- PCB Prototyping: ordering the boards.
- Design, Testing and Troubleshooting: bringing the board up.
FAQ
Should I use a two-layer or four-layer board for a microcontroller?
A two-layer board is fine for slow signals and low pin density if you keep a ground pour and decoupling. Use four layers for USB high speed, fast memory, many pins or low-noise analog circuits.
How do I choose a buck converter inductor?
L = Vout (1 − D) ÷ (f ΔI) for a ripple current of 20 to 40 % of the load, with a saturation current above the peak (load plus half the ripple).
How wide should a USB 2.0 pair be?
About 0.26 mm with 0.15 mm spacing over a 0.21 mm prepreg on FR-4 for 90 Ω differential; ask the fabricator to confirm with their stack-up.
What do I do first when a new board does not work?
Power off: check for shorts on the rails with a meter; inspect the joints; then power with a current-limited supply and check each rail.
Can I copy a layout from a data sheet?
Yes, it is the best starting point: copy the placement and the critical routing, then adjust for your footprints and rules.
References
- IPC-2221B and IPC-2141A; manufacturers’ data sheets and layout guides for the regulator, microcontroller and USB chips.
- USB-IF, Universal Serial Bus Specification 2.0 and the High-Speed USB Platform Design Guidelines.
- Erickson, R. W. and Maksimović, D., Fundamentals of Power Electronics, Springer (buck design equations).
Last reviewed: October 2026. The examples use typical values; always confirm component ratings, impedance and thermal figures against the data sheets and your fabricator.